公开(公告)号：US20180059958A1

公开(公告)日：2018-03-01

申请号：US15252886

申请日：2016-08-31

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  G11C14/00 ,  G11C11/22 ,  G11C11/4096 ,  H01L27/115 ,  H01L49/02 ,  H01L23/528 ,  H01L27/108

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0626 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/068 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/404 ,  G11C11/4096 ,  G11C14/0027 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/55

Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

公开(公告)号：US11853552B2

公开(公告)日：2023-12-26

申请号：US17374359

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  G11C11/404 ,  G11C11/00 ,  H10B12/00 ,  H10B53/30 ,  G11C11/22 ,  G11C11/4096 ,  G11C14/00 ,  H01L23/528 ,  H01L49/02

CPC classification number: G06F3/0611 ,  G06F3/068 ,  G06F3/0625 ,  G06F3/0626 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/404 ,  G11C11/4096 ,  G11C14/0027 ,  H01L23/528 ,  H01L28/55 ,  H10B12/03 ,  H10B12/30 ,  H10B53/30 ,  G11C11/2273 ,  G11C2207/2245

Abstract: The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

公开(公告)号：US11068166B2

公开(公告)日：2021-07-20

申请号：US16358219

申请日：2019-03-19

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  G11C11/404 ,  H01L23/528 ,  H01L27/108 ,  G11C11/00 ,  G11C11/22 ,  G11C11/4096 ,  G11C14/00 ,  H01L27/11507 ,  H01L49/02

Abstract: A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

公开(公告)号：US20190212919A1

公开(公告)日：2019-07-11

申请号：US16358219

申请日：2019-03-19

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  H01L49/02 ,  H01L27/11507 ,  G11C11/22 ,  H01L23/528 ,  H01L27/108 ,  G11C11/404 ,  G11C11/4096 ,  G11C14/00

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0626 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/068 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/404 ,  G11C11/4096 ,  G11C14/0027 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/55

Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

公开(公告)号：US10282108B2

公开(公告)日：2019-05-07

申请号：US15252886

申请日：2016-08-31

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  G11C11/404 ,  H01L49/02 ,  G11C11/22 ,  G11C11/4096 ,  G11C14/00 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507

Abstract: The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

公开(公告)号：US20210405884A1

公开(公告)日：2021-12-30

申请号：US17374359

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Ryan ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Robert Quinn

IPC: G06F3/06 ,  G11C11/404 ,  G11C11/00 ,  G11C11/22 ,  G11C11/4096 ,  G11C14/00 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507 ,  H01L49/02

Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.