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公开(公告)号:US10482954B2
公开(公告)日:2019-11-19
申请号:US15686308
申请日:2017-08-25
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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公开(公告)号:US20170352414A1
公开(公告)日:2017-12-07
申请号:US15686308
申请日:2017-08-25
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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公开(公告)号:US20150144864A1
公开(公告)日:2015-05-28
申请号:US14611011
申请日:2015-01-30
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Lorenzo Fratin
CPC classification number: H01L45/1675 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/1683
Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.
Abstract translation: 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线,并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。
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公开(公告)号:US08975148B2
公开(公告)日:2015-03-10
申请号:US13974641
申请日:2013-08-23
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Lorenzo Fratin
CPC classification number: H01L45/1675 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/1683
Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.
Abstract translation: 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线,并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。
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公开(公告)号:US20150357564A1
公开(公告)日:2015-12-10
申请号:US14828773
申请日:2015-08-18
Applicant: Micron Technology, Inc.
Inventor: Damon E. Van Gerpen , Roberto Bez
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1683
Abstract: A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.
Abstract translation: 相变存储单元具有在其间具有相变材料的第一和第二电极。 相变存储单元没有加热器材料作为第一和第二电极中的任一个的一部分,并且在第一和第二电极和相变材料中的任一个之间没有加热材料。 一种形成具有在其上具有相变材料的第一和第二电极的存储单元的方法包括:利用导电材料将具有导电材料的开口的正面内侧壁布置成包括存储单元的第一电极。 开口的高空外侧衬有介电材料。 相变材料形成在开口的横向内侧且与开口中的导电材料电耦合。 形成电耦合到相变材料的导电第二电极材料。 公开了其他实现。
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公开(公告)号:US20130341587A1
公开(公告)日:2013-12-26
申请号:US13974641
申请日:2013-08-23
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Lorenzo Fratin
IPC: H01L45/00
CPC classification number: H01L45/1675 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/1683
Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.
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公开(公告)号:US20140036583A1
公开(公告)日:2014-02-06
申请号:US14047605
申请日:2013-10-07
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
Abstract translation: 一种具有由相变存储元件(3)和选择开关(4)形成的存储单元(2)的相变存储器件。 由自己的相变存储元件(3)和自己的选择开关(4)形成的参考单元(2a)与待读取的存储单元组(7)相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较,由此补偿存储单元的特性中的任何漂移。
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公开(公告)号:US09779805B2
公开(公告)日:2017-10-03
申请号:US14746483
申请日:2015-06-22
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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公开(公告)号:US09773977B2
公开(公告)日:2017-09-26
申请号:US14828773
申请日:2015-08-18
Applicant: Micron Technology, Inc.
Inventor: Damon E. Van Gerpen , Roberto Bez
CPC classification number: H01L45/1253 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1683
Abstract: A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.
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公开(公告)号:US20150287458A1
公开(公告)日:2015-10-08
申请号:US14746483
申请日:2015-06-22
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
Abstract translation: 一种具有由相变存储元件(3)和选择开关(4)形成的存储单元(2)的相变存储器件。 由自己的相变存储元件(3)和自己的选择开关(4)形成的参考单元(2a)与待读取的存储单元组(7)相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较,由此补偿存储单元的特性中的任何漂移。
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