公开(公告)号：US10020287B2

公开(公告)日：2018-07-10

申请号：US14959500

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Kyle K. Kirby ,  Dewali Ray

IPC: H01L25/04 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/043 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/00014

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

公开(公告)号：US20200381437A1

公开(公告)日：2020-12-03

申请号：US16423684

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Devesh Dadhich Shreeram ,  Srinivasan Balakrishnan ,  Dewali Ray ,  Sanjeev Sapra ,  Paul A. Paduano

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

公开(公告)号：US20200243258A1

公开(公告)日：2020-07-30

申请号：US16258904

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sevim Korkmaz ,  Jian Li ,  Sanjeev Sapra ,  Dewali Ray

IPC: H01G4/008 ,  H01G4/08 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

公开(公告)号：US20160086926A1

公开(公告)日：2016-03-24

申请号：US14959500

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Kyle K. Kirby ,  Dewali Ray

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/043 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/00014

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

Abstract translation: 本文公开了用于微电子管芯的直通互连结构以及相关联的系统和方法。 在一个实施例中，微电子管芯组件包括支撑衬底，至少部分地位于支撑衬底上方的第一微电子管芯，以及至少部分地位于第一管芯上方的第二微电子管芯。 所述第一裸片包括半导体衬底，在所述半导体衬底的一部分上延伸的导电迹线，所述迹线与所述半导体衬底的所述部分之间的衬底焊盘以及穿过所述迹线的穿硅通孔（TSV），所述衬底 衬垫和半导体衬底的部分。 第二管芯经由包括TSV的导电路径电耦合到支撑衬底。

公开(公告)号：US20130276985A1

公开(公告)日：2013-10-24

申请号：US13921022

申请日：2013-06-18

Applicant: Micron Technology, Inc.

Inventor： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC: H01L21/683

CPC classification number: H01L21/6833

Abstract: A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

Abstract translation: 处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。 导体从物理接触暴露的导电电极去除。 电介质材料施加在导电电极上。 在静电接触静电载体的同时对衬底进行处理。 在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。 在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。 还公开了用于保持用于加工的基材和这种组件的静电载体。

公开(公告)号：US11011521B2

公开(公告)日：2021-05-18

申请号：US16423684

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Devesh Dadhich Shreeram ,  Srinivasan Balakrishnan ,  Dewali Ray ,  Sanjeev Sapra ,  Paul A. Paduano

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

公开(公告)号：US10964475B2

公开(公告)日：2021-03-30

申请号：US16258904

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sevim Korkmaz ,  Jian Li ,  Sanjeev Sapra ,  Dewali Ray

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/08

Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

公开(公告)号：US08929052B2

公开(公告)日：2015-01-06

申请号：US13921022

申请日：2013-06-18

Applicant: Micron Technology, Inc.

Inventor： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC: H01L21/683

CPC classification number: H01L21/6833

Abstract: A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

Abstract translation: 处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。 导体从物理接触暴露的导电电极去除。 电介质材料施加在导电电极上。 在静电接触静电载体的同时对衬底进行处理。 在一个实施例中，将导体强制通过电介质材料，该电介质材料被接纳在静电载体的导电电极上，以使导体与导电电极物理接触以将基底静电地接合到静电载体上。 在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。 还公开了用于保持用于加工的基材和这种组件的静电载体。