公开(公告)号：US10424583B2

公开(公告)日：2019-09-24

申请号：US16027598

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L21/336 ,  H01L27/108 ,  H01L27/11582 ,  H01L49/02

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

公开(公告)号：US20190252251A1

公开(公告)日：2019-08-15

申请号：US16391600

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Wen-Chieh Wang ,  Sheng-Wei Yang

IPC: H01L21/768 ,  H01L29/06 ,  H01L27/108 ,  H01L27/11582 ,  H01L21/764 ,  H01L49/02

CPC classification number: H01L21/76895 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76883 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/4991

Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

公开(公告)号：US20180366540A1

公开(公告)日：2018-12-20

申请号：US16110615

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L49/02 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3065 ,  C23C14/10 ,  C23C14/08 ,  C23C14/06 ,  C23C16/06 ,  C23C16/34 ,  H01L29/66 ,  C23C16/40 ,  C23C14/16 ,  H01L29/92 ,  H01L21/304 ,  H01L21/306

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

公开(公告)号：US10008461B2

公开(公告)日：2018-06-26

申请号：US14731426

申请日：2015-06-05

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US20170358583A1

公开(公告)日：2017-12-14

申请号：US15671471

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/11582 ,  H01L28/00

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

公开(公告)号：US09761559B1

公开(公告)日：2017-09-12

申请号：US15135539

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L2224/16145 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06586

Abstract: A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.

公开(公告)号：US09735161B2

公开(公告)日：2017-08-15

申请号：US14848357

申请日：2015-09-09

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/11582 ,  H01L28/00

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

公开(公告)号：US10854514B2

公开(公告)日：2020-12-01

申请号：US16391600

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Wen-Chieh Wang ,  Sheng-Wei Yang

IPC: H01L21/768 ,  H01L21/764 ,  H01L29/06 ,  H01L27/108 ,  H01L27/11582 ,  H01L49/02 ,  H01L29/49

Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

公开(公告)号：US10825783B2

公开(公告)日：2020-11-03

申请号：US16021383

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.

公开(公告)号：US20190326298A1

公开(公告)日：2019-10-24

申请号：US16459002

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L27/108 ,  H01L21/308 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.