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1.发明申请公开(公告)号：US20180205370A1
公开(公告)日：2018-07-19
申请号：US15824139
申请日：2017-11-28
发明人： Qu Gary Jin , Kamran Rahbar
IPC分类号： H03K5/1252 , H03L7/099 , H03L7/091
CPC分类号： H03K5/1252 , H03K2005/00052 , H03K2005/00058 , H03L7/091 , H03L7/0991 , H03L2207/50
摘要： A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+δ at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+Δ at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.
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公开(公告)号：US20170346494A1
公开(公告)日：2017-11-30
申请号：US15597726
申请日：2017-05-17
CPC分类号： H03L7/103 , H03K5/135 , H03K2005/00104 , H03L7/085 , H03L7/091 , H03L7/0991 , H03L7/10 , H03L7/1803 , H03L2207/50
摘要： To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.
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公开(公告)号：US09444474B2
公开(公告)日：2016-09-13
申请号：US14698966
申请日：2015-04-29
发明人： Kamran Rahbar , Qu Gary Jin
CPC分类号： H03L7/099 , H03B5/32 , H03L7/07 , H03L7/093 , H03L7/0991
摘要： A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.
摘要翻译： 具有噪声衰减的多回路锁相环（PLL）系统具有包括本地振荡器的第一PLL，耦合到第一PLL的输出的第二PLL以及第二PLL与第一PLL之间的反馈路径中的第三PLL 。 第一相位比较器将输入信号与第一反馈信号进行比较，以产生用于第一PLL的第一相位误差信号。 第一相位误差信号乘以确定噪声衰减量的缩放因子k。 第三PLL具有比第二PLL优选至少十倍的带宽，使得第二和第三PLL的总体传递函数近似为第二PLL的传递函数。 第三PLL的传递函数乘以缩放因子1 / k。 这种布置允许在第一PLL中使用未补偿的本地振荡器。 在未补偿的本地振荡器中产生的噪声被衰减因子k减小。
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公开(公告)号：US10992301B1
公开(公告)日：2021-04-27
申请号：US16816113
申请日：2020-03-11
发明人： Krste Mitric , Kamran Rahbar
摘要： A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.
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公开(公告)号：US09209965B2
公开(公告)日：2015-12-08
申请号：US14591969
申请日：2015-01-08
发明人： Kamran Rahbar , Peter Crosby
CPC分类号： H04L7/0331 , H03L7/00 , H03L7/093 , H04J3/0697
摘要： A network interface for recovering timing information over packet networks has line card at the edge of a local network and a timing card separate from the line card. A physical interface time-stamps incoming timing packets based on smoothed recovered clock signals. A clock recovery module on the line card generates timing signals from the time-stamped incoming timing packets. A first phase locked generates raw clock signals from the timing signals. A second phase locked loop on the timing card generates the smoothed clock signals from said raw clock signals and applies them to the clock recovery module on the line card.
摘要翻译： 用于通过分组网络恢复定时信息的网络接口具有在本地网络边缘的线路卡和与线路卡分开的定时卡。 物理接口基于平滑的恢复时钟信号对进入的定时分组进行时间戳。 线卡上的时钟恢复模块从时间戳的入站定时包生成定时信号。 第一相锁定从定时信号产生原始时钟信号。 定时卡上的第二个锁相环产生来自所述原始时钟信号的平滑时钟信号，并将它们应用到线路卡上的时钟恢复模块。
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公开(公告)号：US10917097B1
公开(公告)日：2021-02-09
申请号：US16795520
申请日：2020-02-19
发明人： Peter Meyer , Kamran Rahbar , Drew Jenkins
摘要： A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.
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公开(公告)号：US20180091291A1
公开(公告)日：2018-03-29
申请号：US15701749
申请日：2017-09-12
发明人： Tariq Haddad , Kamran Rahbar , Peter Meyer
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/099 , H03L7/0991 , H04J3/0664 , H04J3/0667
摘要： A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.
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公开(公告)号：US20150326232A1
公开(公告)日：2015-11-12
申请号：US14698966
申请日：2015-04-29
发明人： Kamran Rahbar , Qu Gary Jin
CPC分类号： H03L7/099 , H03B5/32 , H03L7/07 , H03L7/093 , H03L7/0991
摘要： A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.
摘要翻译： 具有噪声衰减的多回路锁相环（PLL）系统具有包括本地振荡器的第一PLL，耦合到第一PLL的输出的第二PLL以及第二PLL和第一PLL之间的反馈路径中的第三PLL 。 第一相位比较器将输入信号与第一反馈信号进行比较，以产生用于第一PLL的第一相位误差信号。 第一相位误差信号乘以确定噪声衰减量的缩放因子k。 第三PLL具有比第二PLL优选至少十倍的带宽，使得第二和第三PLL的总体传递函数近似为第二PLL的传递函数。 第三PLL的传递函数乘以缩放因子1 / k。 这种布置允许在第一PLL中使用未补偿的本地振荡器。 在未补偿的本地振荡器中产生的噪声被衰减因子k减小。
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公开(公告)号：US20140320186A1
公开(公告)日：2014-10-30
申请号：US14263170
申请日：2014-04-28
发明人： Q. Gary Jin , Kamran Rahbar , Krste Mitric , Tanmay Zargar
IPC分类号： H03L7/107
CPC分类号： H03L7/1075
摘要： Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modified proportional component is combined with the unmodified integral component to provide the phase error signal.
摘要翻译： 相位斜率控制在锁相环中，其中控制振荡器的相位误差信号通过确定比例分量是否落在由上下限界限的范围内，具有比例分量和积分分量。 如果比例分量落在提供相位误差信号的范围内，则比例分量与积分分量组合。 否则，修正比例分量以满足相位斜率要求，同时不修改积分分量。 修正的比例分量与未修正的积分分量组合以提供相位误差信号。
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公开(公告)号：US10128826B2
公开(公告)日：2018-11-13
申请号：US15824139
申请日：2017-11-28
发明人： Qu Gary Jin , Kamran Rahbar
IPC分类号： H03B21/00 , H03K5/1252 , H03L7/099 , H03L7/091 , H03K5/00
摘要： A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+δ at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+Δ at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.
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