公开(公告)号：US20090230485A1

公开(公告)日：2009-09-17

申请号：US12172603

申请日：2008-07-14

申请人： Mika OKUMURA ,  Makio Horikawa ,  Kimitoshi Satou ,  Yasuo Yamaguchi

发明人： Mika OKUMURA ,  Makio Horikawa ,  Kimitoshi Satou ,  Yasuo Yamaguchi

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： G01P15/0802 ,  B81B2201/0235 ,  B81C1/00182 ,  H01L2924/0002 ,  H01L2924/00

摘要： A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor wafer in which an acceleration sensor is to be formed. After a sacrificial film is stacked on the wiring and processed, a conductive film is stacked on the wiring and processed to form a plurality of thin film structures in the formation region. The recessed portion surrounds the formation region.

摘要翻译： 在第一绝缘膜和第二绝缘膜上设置凹部，第一绝缘膜层叠在半导体晶片上，第二绝缘膜层叠在第一绝缘膜上。 在形成有加速度传感器的半导体晶片的形成区域中对第一绝缘膜和第二绝缘膜进行处理以形成布线。 在牺牲膜堆叠在布线上并处理之后，在布线上堆叠导电膜并加工成在形成区域中形成多个薄膜结构。 凹部包围形成区域。

公开(公告)号：US20070031638A1

公开(公告)日：2007-02-08

申请号：US11276338

申请日：2006-02-24

申请人： Mika OKUMURA ,  Makio Horikawa ,  Kimitoshi Satou

发明人： Mika OKUMURA ,  Makio Horikawa ,  Kimitoshi Satou

IPC分类号： D06N7/04 ,  B05D5/12 ,  G11B5/64 ,  H05K3/00

CPC分类号： G01P15/125 ,  B81B3/0086 ,  B81B2201/0235 ,  G01P15/0802 ,  G01P2015/0814 ,  Y10T428/24355

摘要： The present invention provides a thin film structure configured such that: thin films 8a and 8b and an electrode pad 7 are provided on a substrate 5; and a nonconductive shielding film 11 is formed on the sides of the thin films 8a facing the electrode pad 7 such that the top surface of the shielding film 11 is higher than the top surface of the electrode pad 7. That is, the shielding film 11 covers the top surfaces and sides of the thin films 8a between adjacent electrode pads. This arrangement allows one to reduce the parasitic capacitance between adjacent electrode pads and prevent a change in the characteristics, as well as canceling the fringe effect.

摘要翻译： 本发明提供一种薄膜结构，其构造为：在基板5上设置薄膜8a和8b以及电极垫7; 并且在面对电极焊盘7的薄膜8a的侧面上形成非导电屏蔽膜11，使得屏蔽膜11的顶表面高于电极焊盘7的顶表面。也就是说，屏蔽膜 11覆盖相邻电极焊盘之间的薄膜8a的顶表面和侧面。 这种布置允许减少相邻电极焊盘之间的寄生电容，并且防止特性的改变以及抵消边缘效应。

公开(公告)号：US20090166623A1

公开(公告)日：2009-07-02

申请号：US12164464

申请日：2008-06-30

申请人： Kimitoshi SATO ,  Mika OKUMURA ,  Yasuo YAMAGUCHI ,  Makio HORIKAWA

发明人： Kimitoshi SATO ,  Mika OKUMURA ,  Yasuo YAMAGUCHI ,  Makio HORIKAWA

IPC分类号： H01L29/04 ,  H01L21/20

CPC分类号： G01P15/125 ,  B81B7/007 ,  B81B2207/097 ,  G01P1/023 ,  G01P15/0802 ,  G01P2015/0814

摘要： A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.

摘要翻译： 第一互连沿着基板的凹槽和凹槽的底表面形成，并且具有第一厚度。 第二互连电连接到第一互连并且具有大于第一厚度的第二厚度。 加速度感测单元电连接到第二互连。 密封单元具有与基板相对的部分，其间具有第一互连，并且包围基板上的第二互连和加速度感测单元。 在密封单元上设置盖，以在由密封单元包围的基板的区域上形成空腔。 由此，可以确保空腔的气密性，并且还可以减小与加速度检测单元连接的布线的电阻。

公开(公告)号：US20110042811A1

公开(公告)日：2011-02-24

申请号：US12791228

申请日：2010-06-01

申请人： Mika OKUMURA ,  Makio HORIKAWA ,  Takeshi MURAKAMI

发明人： Mika OKUMURA ,  Makio HORIKAWA ,  Takeshi MURAKAMI

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13055 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, electrodes separated from each other and extending from a first main surface in the direction of depth of the semiconductor substrate, and an interconnect portion coupling the electrodes to each other and extending from the first main surface in the direction of depth of the semiconductor substrate without passing through the semiconductor substrate. One of the electrodes is a through electrode passing through the semiconductor substrate to reach a second main surface. For semiconductor devices having through electrodes and vertically stacked on each other, the interconnect portion serves to enhance the degree of design freedom.

摘要翻译： 半导体器件包括半导体衬底，彼此分离并在半导体衬底的深度方向上从第一主表面延伸的电极和将电极彼此连接并从第一主表面沿着方向 的半导体衬底的深度，而不通过半导体衬底。 其中一个电极是穿过半导体衬底到达第二主表面的通孔。 对于具有通过电极并且彼此垂直堆叠的半导体器件，互连部分用于增强设计自由度。

公开(公告)号：US20110303992A1

公开(公告)日：2011-12-15

申请号：US13025633

申请日：2011-02-11

申请人： Mika OKUMURA ,  Yasuo Yamaguchi ,  Takeshi Murakami

发明人： Mika OKUMURA ,  Yasuo Yamaguchi ,  Takeshi Murakami

IPC分类号： H01L29/84 ,  H01L21/56

CPC分类号： B81B7/0051 ,  B81B2201/0235 ,  B81C2203/0154 ,  G01P1/023 ,  G01P15/0802 ,  G01P15/125 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2924/01019

摘要： A semiconductor device includes a substrate, an element formed on the substrate, a nitride film formed on the substrate, a anti-peel film formed on the nitride film, and a molded resin covering the anti-peel film and the element. The anti-peel film has residual compressive stress.

摘要翻译： 半导体器件包括基板，形成在基板上的元件，在基板上形成的氮化物膜，形成在氮化物膜上的抗剥离膜，以及覆盖抗剥离膜和元件的模制树脂。 抗剥离膜具有残余压应力。