公开(公告)号：US5740119A

公开(公告)日：1998-04-14

申请号：US756505

申请日：1996-11-26

申请人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

发明人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

IPC分类号： G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C29/28 ,  G11C8/12

摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

公开(公告)号：US5867439A

公开(公告)日：1999-02-02

申请号：US22490

申请日：1998-02-12

申请人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

发明人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

IPC分类号： G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C29/28 ,  G11C8/12

摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

摘要翻译： 在选择性地实现4K刷新周期和8K刷新周期之一的半导体存储器件中，外部施加的地址信号位的位置由地址切换电路在内部切换，使得在相同位置的存储单元被选择，而不管4K刷新 循环或8K刷新周期根据刷新周期模式指定信号指定。 因此，通过在一个刷新周期模式下测试器件，可以在两个刷新周期操作中检查器件，减少测试时间并使测试更容易。

公开(公告)号：US06301163B1

公开(公告)日：2001-10-09

申请号：US09385582

申请日：1999-08-27

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C2900

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

摘要翻译： 一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器 正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。 控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。 所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

公开(公告)号：US5764576A

公开(公告)日：1998-06-09

申请号：US752419

申请日：1996-11-19

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

公开(公告)号：US5999464A

公开(公告)日：1999-12-07

申请号：US58885

申请日：1998-04-13

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

公开(公告)号：US5970507A

公开(公告)日：1999-10-19

申请号：US676963

申请日：1996-07-08

申请人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G06F12/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.

摘要翻译： 在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。 从多个刷新周期类型中选择自刷新模式的刷新周期。 多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

公开(公告)号：US5793686A

公开(公告)日：1998-08-11

申请号：US755930

申请日：1996-11-25

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

公开(公告)号：US06400621B2

公开(公告)日：2002-06-04

申请号：US09912518

申请日：2001-07-26

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C700

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

摘要翻译： 一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器 正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。 控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。 所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

公开(公告)号：US5726940A

公开(公告)日：1998-03-10

申请号：US833207

申请日：1997-04-14

申请人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani

发明人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/46 ,  G11C29/34 ,  G11C29/50

摘要： In the semiconductor memory device in accordance with the present invention, when test mode is entered at WCbR+super V.sub.IH +address key timing, the test mode is terminated only at the WCbR+super V.sub.IH +address key timing. Therefore, when refresh is to be started in the test mode, erroneous entrance to another test mode can be prevented, ensuring highly reliable testing. Further, since it is not necessary to take into account the special condition to enter the refreshing operation in the test mode, formation of a test pattern is facilitated.

摘要翻译： 在根据本发明的半导体存储器件中，当以WCbR +超VIH +地址键定时输入测试模式时，测试模式仅在WCbR +超级VIH +地址键定时终止。 因此，当在测试模式下开始刷新时，可以防止对另一测试模式的错误进入，确保高度可靠的测试。 此外，由于不需要考虑在测试模式中进入刷新操作的特殊条件，因此便于形成测试图案。

公开(公告)号：US5953261A

公开(公告)日：1999-09-14

申请号：US76887

申请日：1998-05-13

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

摘要翻译： 与同时选择的多个存储单元相对应地提供的读驱动器被配线或连接到内部读数据总线，内部读数据总线又分别对应于多个存储单元阵列提供。 为内部读取数据总线提供测试模式电路，用于检测这些内部读取数据总线上信号电位逻辑的一致/不一致。 在测试操作中，所有读取驱动器都被激活以读取相应的内部读取数据总线上的选定存储单元数据。