公开(公告)号：US07603543B2

公开(公告)日：2009-10-13

申请号：US11055862

申请日：2005-02-11

申请人： Miles Robert Dooley ,  Scott Bruce Frommer ,  Hung Qui Le ,  Sheldon B. Levenstein ,  Anthony Saporito

发明人： Miles Robert Dooley ,  Scott Bruce Frommer ,  Hung Qui Le ,  Sheldon B. Levenstein ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.

摘要翻译： 一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。 特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

公开(公告)号：US20120297162A1

公开(公告)日：2012-11-22

申请号：US13297199

申请日：2011-11-15

申请人： Miles Robert Dooley ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein

发明人： Miles Robert Dooley ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein

IPC分类号： G06F12/06

CPC分类号： G06F11/362

摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.

摘要翻译： 一种用于以可以使用处理器的关键区域中的最小物理空间来实现的深度流水线处理器设计中的地址匹配的快速检测的方法，装置和算法。 地址比较分为两部分。 第一部分是快速部分地址匹配比较系统。 第二部分是较慢的全地址匹配比较系统。 如果检测到请求的地址和注册表地址之间的部分匹配，则在执行完整的地址匹配检查时暂时停止执行请求地址的程序或指令集。 如果完整的地址匹配检查导致所请求的地址和注册表地址之间的完全匹配，则程序或指令集被中断和停止。 否则，程序或指令集继续执行。

公开(公告)号：US07380062B2

公开(公告)日：2008-05-27

申请号：US11055818

申请日：2005-02-11

申请人： Scott Bruce Frommer ,  Sheldon B. Levenstein ,  Bruce Joseph Ronchetti ,  Anthony Saporito

发明人： Scott Bruce Frommer ,  Sheldon B. Levenstein ,  Bruce Joseph Ronchetti ,  Anthony Saporito

IPC分类号： G06F12/02

CPC分类号： G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0897

摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

公开(公告)号：US20080209177A1

公开(公告)日：2008-08-28

申请号：US12113561

申请日：2008-05-01

申请人： Scott Bruce Frommer ,  Sheldon B. Levenstein ,  Bruce Joseph Ronchetti ,  Anthony Saporito

发明人： Scott Bruce Frommer ,  Sheldon B. Levenstein ,  Bruce Joseph Ronchetti ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0897

摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

公开(公告)号：US20080162887A1

公开(公告)日：2008-07-03

申请号：US12048527

申请日：2008-03-14

申请人： RACHEL MARIE FLOOD ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

发明人： RACHEL MARIE FLOOD ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

IPC分类号： G06F9/30

CPC分类号： G06F9/355 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1027

摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

公开(公告)号：US07360058B2

公开(公告)日：2008-04-15

申请号：US11054274

申请日：2005-02-09

申请人： Rachel Marie Flood ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

发明人： Rachel Marie Flood ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

IPC分类号： G06F12/00

CPC分类号： G06F9/355 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1027

摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

公开(公告)号：US07809924B2

公开(公告)日：2010-10-05

申请号：US12048527

申请日：2008-03-14

申请人： Rachel Marie Flood ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

发明人： Rachel Marie Flood ,  Scott Bruce Frommer ,  David Allen Hrusecky ,  Sheldon B. Levenstein ,  Michael Thomas Vaden

IPC分类号： G06F12/00

CPC分类号： G06F9/355 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1027

摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

公开(公告)号：US07571283B2

公开(公告)日：2009-08-04

申请号：US12113561

申请日：2008-05-01

申请人： Scott B. Frommer ,  Sheldon B. Levenstein ,  Bruce J. Ronchetti ,  Anthony Saporito

发明人： Scott B. Frommer ,  Sheldon B. Levenstein ,  Bruce J. Ronchetti ,  Anthony Saporito

IPC分类号： G06F12/08

CPC分类号： G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0897

摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

公开(公告)号：US20080263283A1

公开(公告)日：2008-10-23

申请号：US12131432

申请日：2008-06-02

申请人： Sheldon B. Levenstein ,  Anthony Saporito

发明人： Sheldon B. Levenstein ,  Anthony Saporito

IPC分类号： G06F12/00

CPC分类号： G06F12/0855

摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.

摘要翻译： 方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。 用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。 如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。 如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。 该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。 该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

公开(公告)号：US07401186B2

公开(公告)日：2008-07-15

申请号：US11054273

申请日：2005-02-09

申请人： Sheldon B. Levenstein ,  Anthony Saporito

发明人： Sheldon B. Levenstein ,  Anthony Saporito

IPC分类号： G06F12/00

CPC分类号： G06F12/0855

摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.

摘要翻译： 方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。 用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。 如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。 如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。 该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。 该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。