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公开(公告)号：US20080162887A1
公开(公告)日：2008-07-03
申请号：US12048527
申请日：2008-03-14
申请人： RACHEL MARIE FLOOD , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： RACHEL MARIE FLOOD , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F9/30
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。
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公开(公告)号：US07360058B2
公开(公告)日：2008-04-15
申请号：US11054274
申请日：2005-02-09
申请人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。
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公开(公告)号：US07809924B2
公开(公告)日：2010-10-05
申请号：US12048527
申请日：2008-03-14
申请人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。
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4.发明申请公开(公告)号：US20120297162A1
公开(公告)日：2012-11-22
申请号：US13297199
申请日：2011-11-15
IPC分类号： G06F12/06
CPC分类号： G06F11/362
摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.
摘要翻译： 一种用于以可以使用处理器的关键区域中的最小物理空间来实现的深度流水线处理器设计中的地址匹配的快速检测的方法，装置和算法。 地址比较分为两部分。 第一部分是快速部分地址匹配比较系统。 第二部分是较慢的全地址匹配比较系统。 如果检测到请求的地址和注册表地址之间的部分匹配，则在执行完整的地址匹配检查时暂时停止执行请求地址的程序或指令集。 如果完整的地址匹配检查导致所请求的地址和注册表地址之间的完全匹配，则程序或指令集被中断和停止。 否则，程序或指令集继续执行。
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5.发明授权Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中获取请求同时运行，而不管其一致等级公开(公告)号：US07284094B2
公开(公告)日：2007-10-16
申请号：US11054293
申请日：2005-02-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译： 一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。 响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。 确定这些识别的未完成的有效提取条目使用的SetID。 所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。 用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。
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6.发明授权Method, apparatus and program product for enhancing performance of an in-order processor with long stalls 失效用于提高具有长档位的处理器性能的方法，装置和程序产品公开(公告)号：US07603543B2
公开(公告)日：2009-10-13
申请号：US11055862
申请日：2005-02-11
申请人： Miles Robert Dooley , Scott Bruce Frommer , Hung Qui Le , Sheldon B. Levenstein , Anthony Saporito
发明人： Miles Robert Dooley , Scott Bruce Frommer , Hung Qui Le , Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.
摘要翻译： 一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。 特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。
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7.发明授权Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品公开(公告)号：US07318127B2
公开(公告)日：2008-01-08
申请号：US11055820
申请日：2005-02-11
IPC分类号： G06F12/14
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译： 在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。 动态分配缓存以在多个线程之间使用。 高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。 高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。 在执行线程期间，可以动态地更改部分的大小。
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8.发明授权Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权机制在多线程微处理器中维护最佳情况需求指令重新分配公开(公告)号：US07380062B2
公开(公告)日：2008-05-27
申请号：US11055818
申请日：2005-02-11
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。
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9.发明申请Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch 有权多线程微处理器中维护最佳案例需求指令重新分配的机制公开(公告)号：US20080209177A1
公开(公告)日：2008-08-28
申请号：US12113561
申请日：2008-05-01
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。
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公开(公告)号：US07092270B2
公开(公告)日：2006-08-15
申请号：US10880719
申请日：2004-06-30
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.
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