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1.发明授权Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权机制在多线程微处理器中维护最佳情况需求指令重新分配公开(公告)号：US07380062B2
公开(公告)日：2008-05-27
申请号：US11055818
申请日：2005-02-11
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。
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2.发明申请Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch 有权多线程微处理器中维护最佳案例需求指令重新分配的机制公开(公告)号：US20080209177A1
公开(公告)日：2008-08-28
申请号：US12113561
申请日：2008-05-01
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译： 一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。 响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。 检查需求缺失的高速缓存行以确定关键部门。 一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。 加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。
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3.发明授权Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中获取请求同时运行，而不管其一致等级公开(公告)号：US07284094B2
公开(公告)日：2007-10-16
申请号：US11054293
申请日：2005-02-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译： 一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。 响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。 确定这些识别的未完成的有效提取条目使用的SetID。 所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。 用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。
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4.发明授权Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品公开(公告)号：US07318127B2
公开(公告)日：2008-01-08
申请号：US11055820
申请日：2005-02-11
IPC分类号： G06F12/14
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译： 在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。 动态分配缓存以在多个线程之间使用。 高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。 高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。 在执行线程期间，可以动态地更改部分的大小。
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5.发明授权公开(公告)号：US07660965B2
公开(公告)日：2010-02-09
申请号：US11969988
申请日：2008-01-07
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。
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6.发明授权公开(公告)号：US07350051B2
公开(公告)日：2008-03-25
申请号：US11054277
申请日：2005-02-09
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译： 一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。 该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。
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7.发明授权Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器公开(公告)号：US07752354B2
公开(公告)日：2010-07-06
申请号：US11055844
申请日：2005-02-11
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译： 控制数据处理系统中的重启界面的管理系统。 管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。 管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。
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8.发明授权公开(公告)号：US06336168B1
公开(公告)日：2002-01-01
申请号：US09259139
申请日：1999-02-26
申请人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1316
CPC分类号： G06F9/30043 , G06F9/3824
摘要： Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.
摘要翻译： 在加载存储单元中执行多个加载指令的流水线和并行执行。 当第一个加载指令引起高速缓存未命中并继续从系统存储器层次结构检索加载数据时，寻址相同加载数据的第二加载指令将被合并到第一加载指令中，以便从系统内存层次结构返回的数据为 发送到注册与第一和第二加载指令相关联的文件。 结果，第二加载指令不必等待，直到在数据高速缓存中写入和验证加载数据。
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9.发明授权公开(公告)号：US06266768B1
公开(公告)日：2001-07-24
申请号：US09213323
申请日：1998-12-16
IPC分类号： G06F738
CPC分类号： G06F9/3834
摘要： In a load/store unit within a microprocessor, load instructions are executed out of order. The load instructions are assigned tags in a predetermined manner, and then assigned to a load reorder queue for keeping track of the program order of the load instructions. Then when new load instructions are issued, the new load instructions are compared to entries within the load reorder queues to detect out of order problems.
摘要翻译： 在微处理器内的加载/存储单元中，加载指令按顺序执行。 加载指令以预定方式分配标签，然后分配给负载重新排序队列，以跟踪加载指令的程序顺序。 然后当发出新的加载指令时，将新的加载指令与加载重新排序队列中的条目进行比较，以检测出乱序问题。
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公开(公告)号：US20100262808A1
公开(公告)日：2010-10-14
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译： 本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。 加载/存储单元在端口接收第一条指令。 响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。 然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。 当第一位被激活时，指令排序单元阻止重新发行的第一条指令。 处理器单元确定第一指令的拒绝类。 指令排序单元启动定时器。 定时器的长度取决于第一条指令的拒绝类型。 指令排序单元重置响应定时器超时的第一位。 响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。
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