CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS
    1.
    发明申请
    CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS 审中-公开
    用于测试半导体器件的电路和方法

    公开(公告)号:US20110102006A1

    公开(公告)日:2011-05-05

    申请号:US12651066

    申请日:2009-12-31

    IPC分类号: G01R31/26 G01R31/3187

    CPC分类号: G01R31/318513

    摘要: A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

    摘要翻译: 一种用于测试半导体装置的电路包括:测试电压施加单元,被配置为响应于测试模式信号将测试电压施加到穿硅通孔(TSV)的第一端;以及检测单元,被配置为连接到第二 结束TSV,并检测从TSV的第二端输出的电流。

    SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF 有权
    半导体装置及其修理方法

    公开(公告)号:US20120194243A1

    公开(公告)日:2012-08-02

    申请号:US13168241

    申请日:2011-06-24

    IPC分类号: H03L7/00

    摘要: A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

    摘要翻译: 半导体装置包括信号传输块和信号接收块。 信号传输块设置在第一芯片中并且被配置为与传输控制信号同步地发送熔丝信息。 信号接收块分别设置在第一芯片和第二芯片中,并被配置为与接收控制信号同步地接收熔丝信息。

    PLASMA DISPLAY APPARATUS
    3.
    发明申请
    PLASMA DISPLAY APPARATUS 失效
    等离子显示设备

    公开(公告)号:US20080088541A1

    公开(公告)日:2008-04-17

    申请号:US11672978

    申请日:2007-02-09

    IPC分类号: G09G3/28

    摘要: A plasma display apparatus comprises a plasma display panel and a driver. The plasma display panel comprises a first electrode, a second electrode, and a third electrode crossing the first electrode and the second electrode. During a first frame, the driver alternately supplies a sustain signal to the first electrode and the second electrode and supplies a constant voltage to the third electrode. During a second frame having a smaller APL of the first frame, the driver alternately supplies a sustain signal to the first electrode and the second electrode and supplies an auxiliary signal to the third electrode so as to correspond to at least one sustain signal of the sustain signals supplied to the first electrode and the second electrode.

    摘要翻译: 等离子体显示装置包括等离子体显示面板和驱动器。 等离子体显示面板包括第一电极,第二电极和与第一电极和第二电极交叉的第三电极。 在第一帧期间,驱动器向第一电极和第二电极交替提供维持信号,并向第三电极提供恒定电压。 在具有第一帧的较小APL的第二帧期间,驱动器交替地向第一电极和第二电极提供维持信号,并将辅助信号提供给第三电极,以便对应于维持的至少一个维持信号 提供给第一电极和第二电极的信号。

    METHOD FOR EXTRACTING PROBABILITY MODEL VALUE FROM PROBABILITY MODEL TABLE AND METHOD AND APPARATUS FOR DECODING SYMBOL VALUE BY USING THE SAME
    4.
    发明申请
    METHOD FOR EXTRACTING PROBABILITY MODEL VALUE FROM PROBABILITY MODEL TABLE AND METHOD AND APPARATUS FOR DECODING SYMBOL VALUE BY USING THE SAME 审中-公开
    从可行性模型表提取概率模型值的方法和使用相同符号来解码符号值的方法和装置

    公开(公告)号:US20110153334A1

    公开(公告)日:2011-06-23

    申请号:US12969616

    申请日:2010-12-16

    IPC分类号: G10L19/00

    摘要: A method for extracting a probability model value from a probability model table and a method and apparatus for decoding a symbol value using the same are provided. The method for extracting a probability model value from a probability model table includes: segmenting and reducing a probability model table including a plurality of probability model values; disposing indexes on the basis of the segmented and reduced probability model table; and searching the probability model table for a probability model value by using the disposed indexes.

    摘要翻译: 提供了一种从概率模型表提取概率模型值的方法,以及用于使用该概率模型表解码符号值的方法和装置。 从概率模型表提取概率模型值的方法包括:分割并减少包括多个概率模型值的概率模型表; 在分段和简化概率模型表的基础上处理指标; 并通过使用所设置的索引来搜索概率模型表中的概率模型值。

    METHOD OF OPTIMIZING PERFORMANCE OF HIERARCHICAL MULTI-CORE PROCESSOR AND MULTI-CORE PROCESSOR SYSTEM FOR PERFORMING THE METHOD
    5.
    发明申请
    METHOD OF OPTIMIZING PERFORMANCE OF HIERARCHICAL MULTI-CORE PROCESSOR AND MULTI-CORE PROCESSOR SYSTEM FOR PERFORMING THE METHOD 审中-公开
    优化分层多核处理器性能的方法和多核处理器系统的执行方法

    公开(公告)号:US20130212594A1

    公开(公告)日:2013-08-15

    申请号:US13617294

    申请日:2012-09-14

    IPC分类号: G06F9/50

    摘要: Disclosed is a multi-core processor, and more particularly, a method of optimizing performance of a multi-core processor having a hierarchical structure and a multi-core processor system for performing the method. To this end, the method of optimizing performance of a hierarchical multi-core processor including a plurality of kernel cores, each kernel core including a plurality of cores sharing a memory, the method includes calculating a correlation between a plurality of threads by a thread correlation managing module within a main processor; grouping the plurality of threads into two or more threads according to information on the calculated correlation by the main processor; and allocating each of the grouped threads within an equal group to each core within an equal kernel core of the hierarchical multi-core processor by a scheduler of the main processor.

    摘要翻译: 公开了一种多核处理器,更具体地,涉及一种优化具有层次结构的多核处理器和用于执行该方法的多核处理器系统的性能的方法。 为此,包括多个内核核心的分级多核处理器的性能优化的方法,每个核心包括共享存储器的多个核,所述方法包括通过线程相关来计算多个线程之间的相关性 主处理器内的管理模块; 根据关于由主处理器计算的相关性的信息,将多个线程分组成两个或更多个线程; 以及通过所述主处理器的调度器将所述分组线程中的每一个分配到所述分层多核处理器的相同内核核心内的相同组内的每个核心。

    SEMICONDUCTOR APPARATUS
    6.
    发明申请

    公开(公告)号:US20120194228A1

    公开(公告)日:2012-08-02

    申请号:US13169430

    申请日:2011-06-27

    申请人: Min Seok CHOI

    发明人: Min Seok CHOI

    IPC分类号: H03B19/00

    摘要: A semiconductor apparatus may include a transmission control signal generation unit, a fuse signal transmission unit, a reception control signal generation unit and a fuse signal reception unit. The transmission control signal generation unit receives a clock signal and generates a plurality of divided clock signals based on the clock signal to output transmission control signals from the plurality of divided clock signals. The fuse signal transmission unit transmits fuse information in synchronization with the transmission control signals. The reception control signal generation unit receives the clock signal and generates the plurality of divided clock signals, and generates reception control signals based on the plurality of divided clock signals. The fuse signal reception unit receives the fuse information in synchronization with the reception control signals.

    摘要翻译: 半导体装置可以包括传输控制信号生成单元,熔丝信号发送单元,接收控制信号生成单元和熔丝信号接收单元。 发送控制信号生成单元接收时钟信号,并根据时钟信号生成多个分频时钟信号,从多个分频时钟信号输出发送控制信号。 熔丝信号传输单元与传输控制信号同步传输熔丝信息。 接收控制信号生成单元接收时钟信号并生成多个分频时钟信号,并且基于多个分频时钟信号产生接收控制信号。 熔丝信号接收部与接收控制信号同步地接收熔丝信息。

    REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    8.
    发明申请
    REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    维修电路和半导体器件包括它们

    公开(公告)号:US20110128072A1

    公开(公告)日:2011-06-02

    申请号:US12836443

    申请日:2010-07-14

    IPC分类号: H01L25/00

    摘要: A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.

    摘要翻译: 半导体装置的修复电路包括发送控制单元,被配置为响应于修复信息信号产生第一至第n(n是等于或大于2的整数)控制信号,并且当第二至第N控制信号 输入指示第m(m为1以上且等于或小于n的整数)TSV的修复信息信号; 传输单元,被配置为响应于第一至第N控制信号,将第一到第n个信号的传输路径分配到第一到第n个TSV和修复TSV; 以及接收单元,被配置为响应于第一至第N控制信号接收从第一至第TSV和修复TSV发送的信号。