公开(公告)号：US20120194243A1

公开(公告)日：2012-08-02

申请号：US13168241

申请日：2011-06-24

申请人： Min Seok CHOI ,  Jong Chern LEE

发明人： Min Seok CHOI ,  Jong Chern LEE

IPC分类号： H03L7/00

CPC分类号： G11C29/025 ,  G11C29/802 ,  G11C2029/4402

摘要： A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

摘要翻译： 半导体装置包括信号传输块和信号接收块。 信号传输块设置在第一芯片中并且被配置为与传输控制信号同步地发送熔丝信息。 信号接收块分别设置在第一芯片和第二芯片中，并被配置为与接收控制信号同步地接收熔丝信息。

公开(公告)号：US20110102006A1

公开(公告)日：2011-05-05

申请号：US12651066

申请日：2009-12-31

申请人： Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

发明人： Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

IPC分类号： G01R31/26 ,  G01R31/3187

CPC分类号： G01R31/318513

摘要： A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

摘要翻译： 一种用于测试半导体装置的电路包括：测试电压施加单元，被配置为响应于测试模式信号将测试电压施加到穿硅通孔（TSV）的第一端;以及检测单元，被配置为连接到第二 结束TSV，并检测从TSV的第二端输出的电流。

公开(公告)号：US20110169542A1

公开(公告)日：2011-07-14

申请号：US12839352

申请日：2010-07-19

申请人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

发明人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

IPC分类号： H03H11/26

CPC分类号： G11C7/22 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

摘要： A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal.

摘要翻译： 半导体存储装置的延迟电路包括：解码单元，被配置为对多个测试信号进行解码并使能多个控制信号中的一个; 偏置电压产生单元，被配置为根据在多个控制信号中使能的控制信号产生第一偏置电压和第二偏置电压; 以及延迟单元，被配置为根据第一和第二偏置电压的电平确定延迟时间，将输入信号延迟所确定的延迟时间，并输出结果信号作为输出信号。

公开(公告)号：US20130234326A1

公开(公告)日：2013-09-12

申请号：US13604481

申请日：2012-09-05

申请人： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

发明人： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

IPC分类号： H01L23/00 ,  H01L21/82

CPC分类号： H01L23/562 ,  H01L21/82 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.

摘要翻译： 半导体装置包括具有贯通硅通孔（TSV）的第一半导体芯片和也具有TSV的第二半导体芯片，其中各个半导体芯片垂直堆叠并通过导电连接构件连接，而无需附加凸块 在导电连接部件和第二半导体芯片之间。

公开(公告)号：US20110103167A1

公开(公告)日：2011-05-05

申请号：US12839345

申请日：2010-07-19

申请人： Kyeong Pil KANG ,  Jong Chern LEE

发明人： Kyeong Pil KANG ,  Jong Chern LEE

IPC分类号： G11C7/06

CPC分类号： G11C7/062 ,  G11C7/1069 ,  G11C7/1096

摘要： A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation.

摘要翻译： 半导体存储装置的本地读出放大器包括：读取放大单元，被配置为在读取操作期间放大第一数据线的数据并将放大的数据传送到第二数据线; 以及写入放大单元，被配置为在写入操作期间放大第二数据线的数据并将放大的数据传送到第一数据线。

公开(公告)号：US20120119764A1

公开(公告)日：2012-05-17

申请号：US13181921

申请日：2011-07-13

申请人： Tae Sik YUN ,  Jong Chern LEE

发明人： Tae Sik YUN ,  Jong Chern LEE

IPC分类号： G01R31/00

CPC分类号： G01R31/31724 ,  G11C29/14 ,  G11C29/46 ,  G11C29/78 ,  G11C29/802

摘要： Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

摘要翻译： 公开了半导体装置的测试模式控制电路的各种实施例及相关方法。 在一个示例性实施例中，测试模式控制电路可以包括：测试模式控制块，被配置为响应于顺序地输入的第一地址信号组和第二地址信号组而产生多个控制信号集; 测试模式传送块，被配置为将根据所述多个控制信号组的组合产生的多个测试模式信号传送到所述半导体装置的多个电路块; 以及配置成将多个控制信号组发送到测试模式传送块的多个全局线。

公开(公告)号：US20110204950A1

公开(公告)日：2011-08-25

申请号：US12970623

申请日：2010-12-16

申请人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

发明人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/05

摘要： A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

摘要翻译： 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。

公开(公告)号：US20090066371A1

公开(公告)日：2009-03-12

申请号：US11964243

申请日：2007-12-26

申请人： Je Yoon KIM ,  Jong Chern LEE

发明人： Je Yoon KIM ,  Jong Chern LEE

IPC分类号： H03K3/00

CPC分类号： H03K5/2481 ,  H03K19/018578

摘要： The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.

摘要翻译： 本发明涉及一种半导体存储器件的缓冲电路，包括一个公共偏置电源单元和多个具有差分放大结构的接口单元。 每个接口单元接收输入信号并差分地放大输入信号和公共偏压。 公共偏置电源单元由参考电压驱动，以向每个接口单元提供公共偏置信号。 缓冲电路使得可以减小半导体存储器件中的缓冲电路占用的面积。

公开(公告)号：US20130241054A1

公开(公告)日：2013-09-19

申请号：US13604449

申请日：2012-09-05

申请人： Chul KIM ,  Jong Chern LEE

发明人： Chul KIM ,  Jong Chern LEE

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

摘要翻译： 在半导体装置中，包括贯通硅通孔的多个半导体芯片在垂直方向堆叠，其中形成在每个半导体芯片中的贯通硅通孔突出超过每个半导体芯片的高度。

公开(公告)号：US20100283518A1

公开(公告)日：2010-11-11

申请号：US12493831

申请日：2009-06-29

申请人： Seung Joon AHN ,  Jong Chern LEE

发明人： Seung Joon AHN ,  Jong Chern LEE

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/0814 ,  H03K5/131 ,  H03K2005/00234

摘要： A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal.

摘要翻译： 半导体集成电路的延迟装置包括：控制信号生成单元，被配置为响应延迟控制信号产生块控制信号和单元控制信号; 多个延迟块，其彼此串联连接，并且被配置为通过延迟输入时钟信号来产生延迟时钟信号，其中每个延迟块包括预定数量的单位延迟器，并且所述多个延迟块是 被配置为响应于所述块控制信号被选择性地激活; 以及包括预定数量的单位延迟器的分钟延迟单元，并且被配置为通过响应于单元控制信号调整所提供的单位延迟器的激活数来延迟延迟时钟信号来产生输出时钟信号。