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    Dual polysilicon gate of a semiconductor device with a multi-plane channel
    1.
    发明授权
    Dual polysilicon gate of a semiconductor device with a multi-plane channel 失效
    具有多平面通道的半导体器件的双多晶硅栅极

    公开(公告)号：US08471338B2

    公开(公告)日：2013-06-25

    申请号：US12632736

    申请日：2009-12-07

    申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7831 ,  H01L21/2256 ,  H01L21/28035 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

    摘要翻译： 半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，形成在衬底的第一区域中的凹陷结构的沟道区，在衬底上形成的栅极绝缘层， 并且形成在所述第一和第二区域的所述栅极绝缘层之上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层， 在通道区域的第一多晶硅层的内部。

    Method for fabricating semiconductor device
    4.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07687389B2

    公开(公告)日：2010-03-30

    申请号：US11448678

    申请日：2006-06-08

    申请人： Kwan-Yong Lim ,  Min-Gyu Sung ,  Heung-Jae Cho ,  Hong-Seon Yang

    发明人： Kwan-Yong Lim ,  Min-Gyu Sung ,  Heung-Jae Cho ,  Hong-Seon Yang

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28247

    摘要： A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.

    摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成第一栅极导电层，在第一栅极导电层上形成阻挡金属，依次形成第二栅极导电层和栅极 图案化栅极硬掩模，第二栅极导电层，势垒金属，第一栅极导电层和栅极绝缘层以形成栅极图案，并且执行等离子体选择性栅极再氧化工艺 在门模式上。

    Semiconductor device and method for fabricating the same
    9.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08021969B2

    公开(公告)日：2011-09-20

    申请号：US11966435

    申请日：2007-12-28

    申请人： Min-Gyu Sung ,  Heung-Jae Cho ,  Kwan-Yong Lim

    发明人： Min-Gyu Sung ,  Heung-Jae Cho ,  Kwan-Yong Lim

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247

    摘要： A method for fabricating a semiconductor device includes forming a stacked layer including a tungsten layer, forming a hard mask pattern over the stacked layer, and oxidizing a surface of the hard mask pattern to form a stress buffer layer. A portion of the stacked layer uncovered by the hard mask pattern is removed using the hard mask pattern and the stress buffer layer as an etch mask, thereby forming a first resultant structure. A capping layer is formed over the first resultant structure, the capping layer is etched to retain the capping layer on sidewalls of the first resultant structure, and the remaining portion of the stacked layer uncovered by the hard mask pattern is removed.

    摘要翻译： 一种制造半导体器件的方法包括：形成包含钨层的堆叠层，在层叠层上形成硬掩模图案，并且氧化硬掩模图案的表面以形成应力缓冲层。 使用硬掩模图案和应力缓冲层作为蚀刻掩模去除未被硬掩模图案覆盖的堆叠层的一部分，从而形成第一结果结构。 在第一结果结构上形成覆盖层，蚀刻覆盖层以将覆盖层保持在第一结构结构的侧壁上，并且去除未被硬掩模图案覆盖的堆叠层的剩余部分。

    Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel
    10.
    发明授权
    Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel 失效
    制造具有多平面通道的半导体器件的双重多晶硅栅极的方法

    公开(公告)号：US07629219B2

    公开(公告)日：2009-12-08

    申请号：US11618779

    申请日：2006-12-30

    申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7831 ,  H01L21/2256 ,  H01L21/28035 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

    摘要翻译： 半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，形成在衬底的第一区域中的凹陷结构的沟道区，在衬底上形成的栅极绝缘层， 并且形成在所述第一和第二区域的所述栅极绝缘层之上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层， 在通道区域的第一多晶硅层的内部。