公开(公告)号：US08610493B2

公开(公告)日：2013-12-17

申请号：US13243955

申请日：2011-09-23

申请人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

发明人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

IPC分类号： G05F3/02

CPC分类号： H03F3/45475 ,  H03F2203/45248 ,  H03F2203/45514 ,  H03F2203/45541 ,  H03F2203/45551

摘要： Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

摘要翻译： 公开了一种偏置电路，其包括被配置为使用参考电流和可变电流产生偏置电压的偏置电压产生部件; 参考电流源部，被配置为将所述参考电流提供给所述偏置电压产生部; 以及电流调节部，被配置为向所述偏置电压生成部提供所述可变电流，并且根据至少两个输入信号的电压电平来调整所述可变电流的量。 偏置电路可以防止功耗的增加，同时提高转换速率。

公开(公告)号：US08542139B2

公开(公告)日：2013-09-24

申请号：US13310606

申请日：2011-12-02

申请人： Min-Hyung Cho ,  Yi-Gyeong Kim ,  Jong-Kee Kwon

发明人： Min-Hyung Cho ,  Yi-Gyeong Kim ,  Jong-Kee Kwon

IPC分类号： H03M1/00

CPC分类号： H03K17/04106 ,  H03M1/06 ,  H03M1/66

摘要： Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.

摘要翻译： 提供了产生用于驱动电流开关的信号的电流开关驱动电路和使用该电流开关的数模转换器。 电流开关驱动电路包括：第一PMOS晶体管，源极端子连接到电源端子，栅极端子接收输入信号，漏极端子输出驱动信号;漏极端子连接的NMOS晶体管 到第一PMOS晶体管的漏极端子，并且栅极端子接收输入信号;第二PMOS晶体管，其源极端子连接到NMOS晶体管的源极端子，栅极端子连接到偏置电压端子， 并且漏极端子连接到接地端子，并且使得允许第二PMOS晶体管恒定地处于导通状态的控制电流源。

公开(公告)号：US09077287B2

公开(公告)日：2015-07-07

申请号：US13531437

申请日：2012-06-22

申请人： Yi-Gyeong Kim ,  Min-Hyung Cho ,  Tae Moon Roh ,  Jong-Kee Kwon ,  Woo Seok Yang ,  Jongdae Kim

发明人： Yi-Gyeong Kim ,  Min-Hyung Cho ,  Tae Moon Roh ,  Jong-Kee Kwon ,  Woo Seok Yang ,  Jongdae Kim

IPC分类号： H03F99/00 ,  H03F3/08

CPC分类号： H03F3/08

摘要： Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

摘要翻译： 公开了一种声音检测电路，其包括：感测单元，被配置为响应于声音信号的声压级产生AC信号; 放大单元，被配置为放大AC信号; 以及偏置电压产生单元，被配置为产生要提供给所述放大单元的偏置电压。 偏置电压产生单元包括被配置为提供功率电流的电流源; 以及电流电压转换电路，被配置为将功率电流转换成偏置电压并且减少由于功率电流引起的噪声。

公开(公告)号：US08482443B2

公开(公告)日：2013-07-09

申请号：US13184182

申请日：2011-07-15

申请人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

发明人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

IPC分类号： H03M3/00

CPC分类号： H03M3/372 ,  H03M3/458

摘要： Provided is a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator. The clock timing adjustment device includes a power detection unit and a timing adjustment unit. The power detection unit receives input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detects powers of the input signals, and outputs a control signal corresponding to a clock time difference where the power is minimized. The timing adjustment unit receives a reference clock and the control signal and outputs the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal.

摘要翻译： 提供了一种用于调整时钟的时间差和Δ-Σ调制器的时钟定时调整装置。 时钟定时调整装置包括功率检测单元和定时调整单元。 功率检测单元接收使用具有多个时钟时间差的第一和第二时钟对生成的输入信号，并分别对应于时钟时间差，检测输入信号的功率，并输出对应于时钟时间的控制信号 功率最小化的差异。 定时调整单元接收参考时钟和控制信号，并根据控制信号从参考时钟输出具有最小功率的时钟时间差的第一和第二时钟。

公开(公告)号：US20120154028A1

公开(公告)日：2012-06-21

申请号：US13243955

申请日：2011-09-23

申请人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

发明人： Yi-Gyeong Kim ,  Bong Chan Kim ,  Min-Hyung Cho ,  Jong-Kee Kwon

IPC分类号： G05F1/10

CPC分类号： H03F3/45475 ,  H03F2203/45248 ,  H03F2203/45514 ,  H03F2203/45541 ,  H03F2203/45551

摘要： Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

摘要翻译： 公开了一种偏置电路，其包括被配置为使用参考电流和可变电流产生偏置电压的偏置电压产生部件; 参考电流源部，被配置为将所述参考电流提供给所述偏置电压产生部; 以及电流调节部，被配置为向所述偏置电压生成部提供所述可变电流，并且根据至少两个输入信号的电压电平来调整所述可变电流的量。 偏置电路可以防止功耗的增加，同时提高转换速率。

公开(公告)号：US07212585B2

公开(公告)日：2007-05-01

申请号：US10734574

申请日：2003-12-12

申请人： Min-Hyung Cho ,  Seung-Chul Lee ,  Mun-Yang Park

发明人： Min-Hyung Cho ,  Seung-Chul Lee ,  Mun-Yang Park

IPC分类号： H04L27/04 ,  H04L27/20 ,  H04B17/00

CPC分类号： H04L27/365 ,  H03C3/40

摘要： There is provided a quadrature modulation transmitter which is capable of solving several problems of the conventional transmitter while performing the same function as the heterodyne transmitter or the digital IF transmitter, in which a circuit structure is simplified and a power consumption is reduced compared with the conventional transmitter. The quadrature modulation transmitter includes: a digital processing block for receiving an I-channel data, a Q-channel data and a clock signal, modulating the I-channel data or an inverted I-channel data into a first analog signal by means of an I-channel DAC according to a switching of an I-clock signal identical to the clock signal, and modulating the Q-channel data and an inverted Q-channel data into a second analog signal by means of a Q-channel DAC according to a switching of a Q-clock signal, the Q-clock signal being an inverted clock signal; and an analog processing block for receiving the first and second analog signals from the digital processing block, adding the first and second analog signals, converting the added signal into an RF domain signal through a mixing operation, and amplifying and transmitting the RF domain signal.

摘要翻译： 提供了一种正交调制发射机，其能够解决传统发射机的几个问题，同时执行与外差发射机或数字IF发射机相同的功能，其中电路结构被简化并且功耗相比于常规发射机 发射机。 正交调制发射机包括：数字处理块，用于接收I信道数据，Q信道数据和时钟信号，通过以下方式将I信道数据或反相I信道数据调制成第一模拟信号 I沟道DAC根据与时钟信号相同的I时钟信号的切换，并且通过根据下述的Q信道DAC将Q通道数据和反相Q通道数据调制成第二模拟信号 Q时钟信号的切换，Q时钟信号是反相时钟信号; 以及模拟处理块，用于从数字处理块接收第一和第二模拟信号，添加第一和第二模拟信号，通过混合操作将相加的信号转换成RF域信号，以及放大和发射RF域信号。

公开(公告)号：US07030799B2

公开(公告)日：2006-04-18

申请号：US11024396

申请日：2004-12-27

申请人： Seung-Chul Lee ,  Min-Hyung Cho ,  Chong-Ki Kwon

发明人： Seung-Chul Lee ,  Min-Hyung Cho ,  Chong-Ki Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/682 ,  H03M1/747

摘要： Disclosed is a current-steering digital-to-analog converter (DAC) which comprises a decoder for receiving an N-bit digital input signal and converting the same into first and second (N−1)-bit digital signals, M (=2N−1) current cells for supplying the current based on the two digital signals, a current cell driver for generating a first analog voltage and a second analog voltage corresponding to the currents based on the two (N−1)-bit digital signals by control of a first clock signal and a second clock signal, and an amplifying circuit for sampling and holding the first and second analog voltage with reference to the first and second clock signals to generate a glitch-removed signal.

公开(公告)号：US20060012501A1

公开(公告)日：2006-01-19

申请号：US11024396

申请日：2004-12-27

申请人： Seung-Chul Lee ,  Min-Hyung Cho ,  Chong-Ki Kwon

发明人： Seung-Chul Lee ,  Min-Hyung Cho ,  Chong-Ki Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/682 ,  H03M1/747

摘要： Disclosed is a current-steering digital-to-analog converter (DAC) which comprises a decoder for receiving an N-bit digital input signal and converting the same into first and second (N-1)-bit digital signals, M (=2N-1) current cells for supplying the current based on the two digital signals, a current cell driver for generating a first analog voltage and a second analog voltage corresponding to the currents based on the two (N-1)-bit digital signals by control of a first clock signal and a second clock signal, and an amplifying circuit for sampling and holding the first and second analog voltage with reference to the first and second clock signals to generate a glitch-removed signal.

摘要翻译： 公开了一种电流转向数模转换器（DAC），其包括用于接收N位数字输入信号并将其转换为第一和第（N-1）位数字信号的解码器，M（= 2 用于基于两个数字信号提供电流的当前单元，用于产生基于两个数字信号的电流对应的第一模拟电压和第二模拟电压的当前单元驱动器， 1）数字信号，以及用于参考第一和第二时钟信号对第一和第二模拟电压进行采样和保持的放大电路，以产生毛刺去除信号。