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16 条记录 (耗时 0.032 秒)

    Copper etch scheme for copper interconnect structure
    2.
    发明授权
    Copper etch scheme for copper interconnect structure 有权
    铜互连结构的铜蚀刻方案

    公开(公告)号：US08735278B2

    公开(公告)日：2014-05-27

    申请号：US13550951

    申请日：2012-07-17

    申请人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

    发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

    摘要翻译： 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    3.
    发明申请
    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
    半导体集成电路制造方法

    公开(公告)号：US20140065818A1

    公开(公告)日：2014-03-06

    申请号：US13599764

    申请日：2012-08-30

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

    Method of semiconductor integrated circuit fabrication
    5.
    发明授权
    Method of semiconductor integrated circuit fabrication 有权
    半导体集成电路制造方法

    公开(公告)号：US08835304B2

    公开(公告)日：2014-09-16

    申请号：US13599764

    申请日：2012-08-30

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    7.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08106512B2

    公开(公告)日：2012-01-31

    申请号：US12845852

    申请日：2010-07-29

    申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    8.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08013445B2

    公开(公告)日：2011-09-06

    申请号：US12112405

    申请日：2008-04-30

    申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

    发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers.

    摘要翻译： 半导体接触结构包括形成在双镶嵌，单镶嵌或形成在电介质材料中的其它开口的铜塞，并且包括铜塞与开口的侧壁和底部之间的复合阻挡层。 复合阻挡层优选地包括设置在开口的底部和侧面上的ALD TaN层，尽管可以使用其它合适的ALD层。 阻挡材料设置在铜塞和ALD层之间。 阻挡层可以是基于Mn的阻挡层，Cr基阻挡层，V基阻挡层，Nb基阻挡层，Ti基阻挡层或其它合适的阻挡层。

    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE
    10.
    发明申请
    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
    低电阻高可靠性接触半导体器件的金属线结构

    公开(公告)号：US20110024908A1

    公开(公告)日：2011-02-03

    申请号：US12845852

    申请日：2010-07-29

    申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。