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公开(公告)号:USD687960S1
公开(公告)日:2013-08-13
申请号:US29432064
申请日:2012-09-13
申请人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
设计人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
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公开(公告)号:USD673688S1
公开(公告)日:2013-01-01
申请号:US29403208
申请日:2011-10-03
申请人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
设计人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
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公开(公告)号:USD668346S1
公开(公告)日:2012-10-02
申请号:US29403211
申请日:2011-10-03
申请人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
设计人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
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公开(公告)号:USD687939S1
公开(公告)日:2013-08-13
申请号:US29432058
申请日:2012-09-13
申请人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
设计人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
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公开(公告)号:USD673687S1
公开(公告)日:2013-01-01
申请号:US29403206
申请日:2011-10-03
申请人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
设计人: Ming Zeng , Stephanie F. Berez , Tylor Garland , Aldis Rauda
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公开(公告)号:USD636888S1
公开(公告)日:2011-04-26
申请号:US29368397
申请日:2010-08-23
申请人: Jason Nikitczuk , Bruce Weiss , Ming Zeng , Tylor Garland , Aldis Rauda
设计人: Jason Nikitczuk , Bruce Weiss , Ming Zeng , Tylor Garland , Aldis Rauda
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公开(公告)号:USD638134S1
公开(公告)日:2011-05-17
申请号:US29368396
申请日:2010-08-23
申请人: Jason Nikitczuk , Bruce Weiss , Ming Zeng , Tylor Garland , Aldis Rauda
设计人: Jason Nikitczuk , Bruce Weiss , Ming Zeng , Tylor Garland , Aldis Rauda
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公开(公告)号:US06970029B2
公开(公告)日:2005-11-29
申请号:US10751135
申请日:2003-12-30
申请人: Bheem Patel , Ming Zeng , Tsung-Chuan Whang
发明人: Bheem Patel , Ming Zeng , Tsung-Chuan Whang
IPC分类号: G01R31/317 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号: G01R31/31727 , H03K5/133 , H03K2005/00052 , H03K2005/00065 , H03L7/0812
摘要: A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.
摘要翻译: 可变延迟信号发生器电路包括延迟链和内插器电路。 延迟链产生多个多相信号,其中每个多相信号表示输入事件信号的延迟版本。 每个多相信号通过第一相位增量与连续信号分离。 内插器电路包括多个内插器块,其中每个块接收多相信号。 内插器电路在连续的内插器块之间内插,以产生表示输入事件信号的修改延迟版本的输出信号。 输出信号被延迟到存在于连续多相信号之间的多个相位延迟中的一个。 为了产生输出信号,基于电流源选择信号来调整每个内插器块内的可变电流源。 电流源选择信号由包括分流电源的偏置电路产生。
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9.
公开(公告)号:US06777975B1
公开(公告)日:2004-08-17
申请号:US09451684
申请日:1999-11-30
申请人: Sanjay Dabral , Ming Zeng , Ramesh Senthinathan , Andrew M. Volk
发明人: Sanjay Dabral , Ming Zeng , Ramesh Senthinathan , Andrew M. Volk
IPC分类号: H03K1716
CPC分类号: G06F13/4086
摘要: A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.
摘要翻译: 一种总线,其中传输线由具有连接到传输线并且具有核心电压VCC的源的pMOSFET激发,并且其中传输线由连接到地的设备终止。
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10.
公开(公告)号:US06601196B1
公开(公告)日:2003-07-29
申请号:US09608449
申请日:2000-06-29
申请人: Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
发明人: Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
IPC分类号: G06F1100
CPC分类号: G06F11/221
摘要: An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.
摘要翻译: 一种用于调试总线的装置和方法,包括插入监视总线上的两个设备之间传输的数据的设备,使得总线被分成两个总线,当数据被复制以传输到诊断设备时,数据在 两辆巴士。
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