利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

64 条记录 (耗时 0.029 秒)

    Cost-effective gate replacement process
    2.
    发明授权
    Cost-effective gate replacement process 有权
    具有成本效益的门更换过程

    公开(公告)号：US08753931B2

    公开(公告)日：2014-06-17

    申请号：US13440848

    申请日：2012-04-05

    申请人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

    发明人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/092

    CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成第一栅极结构和第二栅极结构。 第一和第二栅极结构各自包括位于衬底上方的高k电介质层，位于高k电介质层上方的覆盖层，位于覆盖层上方的N型功函数金属层和位于 超过N型功函金属层。 该方法包括在衬底，第一栅极结构和第二栅极结构之上形成层间电介质（ILD）层。 该方法包括抛光ILD层，直到ILD层的表面与第一栅极结构和第二栅极结构的表面基本上共面。 该方法包括用金属栅极替换第二栅极结构的部分。 然后对半导体器件执行硅化处理。

    DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS
    3.
    发明申请
    DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS 有权
    用于高K和金属盖板的装置和方法

    公开(公告)号：US20130299913A1

    公开(公告)日：2013-11-14

    申请号：US13469645

    申请日：2012-05-11

    申请人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

    发明人： Jyun-Ming Lin ,  Wei Cheng Wu ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

    IPC分类号： H01L27/092 ,  H01L21/283

    CPC分类号： H01L21/823842 ,  H01L21/823857

    摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

    摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

    METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE 有权
    制造金属栅极半导体器件的方法

    公开(公告)号：US20130260547A1

    公开(公告)日：2013-10-03

    申请号：US13434344

    申请日：2012-03-29

    申请人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

    发明人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

    摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

    摘要翻译： 一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。 在栅介质层上形成三层元件。 三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。 使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。 第一覆盖层可以是用于图案化金属栅极层的牺牲层。

    Method of fabricating a metal gate semiconductor device
    6.
    发明授权
    Method of fabricating a metal gate semiconductor device 有权
    制造金属栅极半导体器件的方法

    公开(公告)号：US09209089B2

    公开(公告)日：2015-12-08

    申请号：US13434344

    申请日：2012-03-29

    申请人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

    发明人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

    IPC分类号： H01L21/3205 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

    摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

    摘要翻译： 一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。 在栅介质层上形成三层元件。 三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。 使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。 第一覆盖层可以是用于图案化金属栅极层的牺牲层。

    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT
    7.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT 有权
    改善门接触的方法和装置

    公开(公告)号：US20120001259A1

    公开(公告)日：2012-01-05

    申请号：US12830107

    申请日：2010-07-02

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

    摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

    摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

    Method and device with gate structure formed over the recessed top portion of the isolation structure
    10.
    发明授权
    Method and device with gate structure formed over the recessed top portion of the isolation structure 有权
    具有栅极结构的方法和装置形成在隔离结构的凹入的顶部上

    公开(公告)号：US08329521B2

    公开(公告)日：2012-12-11

    申请号：US12830107

    申请日：2010-07-02

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    IPC分类号： H01L21/8238 ,  H01L27/148

    CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

    摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

    摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。