公开(公告)号：US07554159B2

公开(公告)日：2009-06-30

申请号：US11045300

申请日：2005-01-31

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC分类号： H01L23/62

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

摘要翻译： 一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域， 限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

公开(公告)号：US20050127445A1

公开(公告)日：2005-06-16

申请号：US11045300

申请日：2005-01-31

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/01 ,  H01L27/02 ,  H01L31/0392 ,  H02H9/00

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

摘要翻译： 一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域， 限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

公开(公告)号：US06882009B2

公开(公告)日：2005-04-19

申请号：US10230055

申请日：2002-08-29

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L21/01 ,  H01L23/62

CPC分类号： H01L27/0277 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0716 ,  H01L29/1079 ,  H01L29/1087 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

公开(公告)号：US07092227B2

公开(公告)日：2006-08-15

申请号：US10230287

申请日：2002-08-29

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang

IPC分类号： H02H9/00 ,  H02H3/22 ,  H01L27/01

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection circuit includes a first terminal, a second terminal, an electrostatic discharge device coupled between the first and second terminals, and an active device coupled to the electrostatic discharge device and controlling an electrostatic current through the electrostatic discharge device. The electrostatic discharge device includes at least one of an SCR, an FOD, an active device, a BJT, and an MOS device.

摘要翻译： 静电放电保护电路包括第一端子，第二端子，耦合在第一和第二端子之间的静电放电装置，以及耦合到静电放电装置的有源装置，并且控制通过静电放电装置的静电电流。 静电放电装置包括SCR，FOD，有源器件，BJT和MOS器件中的至少一个。

公开(公告)号：US06465283B1

公开(公告)日：2002-10-15

申请号：US09654810

申请日：2000-09-05

申请人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

发明人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

IPC分类号： H01L21332

CPC分类号： H01L21/823814 ,  H01L21/823878 ,  H01L27/0921

摘要： A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

摘要翻译： 使用闭锁注入来提高CMOS电路中的闭锁抑制的结构和制造方法。 通过在寄生SCR的阴极和阳极上执行离子注入工艺来提高寄生SCR导通路径的阻抗，这可能引起闩锁现象。 因此，寄生SCR因此不容易以更高的抗噪声进行。 因此，可以提高闩锁抗扰度。 此外，可以进行离子注入工艺以实现防止闩锁效应的目的，而不消耗更多的布局面积，从而大大增强了电路设计的灵活性。

公开(公告)号：US06633068B2

公开(公告)日：2003-10-14

申请号：US09852234

申请日：2001-05-10

申请人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure contiguous with the well region, a second isolation structure contiguous with well region and spaced apart from the first isolation structure, a dielectric layer disposed over the well region and the first and second isolation structures, and a layer of silicon, formed over the dielectric layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion, and a second n-type portion contiguous with the second p-type portion, wherein at least a portion of the first p-type and first n-type portions overlap the first isolation structure and at least a portion of the second p-type and second n-type portions overlap the second isolation structure.

摘要翻译： 一种集成电路器件，包括半导体衬底，形成在半导体衬底内部的阱区，与阱区邻接的第一隔离结构，与阱区邻接并与第一隔离结构隔开的第二隔离结构，设置介电层 在所述阱区域和所述第一和第二隔离结构之上，以及形成在所述介电层上的包括第一p型部分，与所述第一p型部分邻接的第一n型部分的硅层，第二p 型部分和与第二p型部分邻接的第二n型部分，其中第一p型和第n型部分的至少一部分与第一隔离结构重叠，并且第二p型部分的至少一部分 p型和第二n型部分与第二隔离结构重叠

公开(公告)号：US20050219780A1

公开(公告)日：2005-10-06

申请号：US11137173

申请日：2005-05-25

申请人： Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Chyh-Yih Chang ,  Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L23/58 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device for electrostatic discharge protection that includes a semiconductor substrate, a lightly doped region of a first dopant type formed in the substrate, a first diffusion region of the first dopant type formed at least partially in the lightly doped region, a second diffusion region of the first dopant type formed at least partially in the lightly doped region and spaced apart from the first diffusion region, a resistive path defined by the lightly doped region, the first and the second diffusion regions, and a third diffusion region of a second dopant type formed in the lightly doped region, and disposed between and spaced apart from the first and the second diffusion regions, wherein the third diffusion region keeps the resistive path at a low resistive state until a normal operation period occurs.

摘要翻译： 一种用于静电放电保护的集成电路装置，包括半导体衬底，形成在衬底中的第一掺杂剂类型的轻掺杂区域，至少部分形成在轻掺杂区域中的第一掺杂剂类型的第一扩散区，第二扩散 所述第一掺杂剂类型的区域至少部分地形成在所述轻掺杂区域中并且与所述第一扩散区间隔开;由所述轻掺杂区域，所述第一和第二扩散区域以及第二扩散区域的第三扩散区域限定的电阻路径 掺杂剂类型形成在轻掺杂区域中，并且设置在第一和第二扩散区域之间并与第一和第二扩散区域间隔开，其中第三扩散区域将电阻路径保持在低电阻状态直到发生正常操作周期。

公开(公告)号：US06576974B1

公开(公告)日：2003-06-10

申请号：US10094814

申请日：2002-03-12

申请人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H01L2900

CPC分类号： H01L29/7317 ,  H01L27/0259 ,  Y10S977/936

摘要： An integrated circuit device receiving signals from a signal pad that includes at least one silicon bipolar junction transistor responsive to the signals from the signal pad for providing electrostatic discharge protection, and a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one silicon bipolar junction transistor, wherein the at least one silicon bipolar junction transistor includes an emitter, collector and base formed in a single silicon layer and isolated from a substrate of the integrated circuit device, and wherein the base is coupled to the detection circuit to receive the bias voltage.

摘要翻译： 接收来自信号焊盘的信号的集成电路装置，其响应于来自信号焊盘的用于提供静电放电保护的信号而包括至少一个硅双极结型晶体管，以及检测电路，用于检测来自信号焊盘的信号并提供偏置电压 到所述至少一个硅双极结型晶体管，其中所述至少一个硅双极结型晶体管包括形成在单个硅层中并与所述集成电路器件的衬底隔离的发射极，集电极和基极，并且其中所述基极耦合到 检测电路接收偏置电压。

公开(公告)号：US07253453B2

公开(公告)日：2007-08-07

申请号：US10442261

申请日：2003-05-21

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang

IPC分类号： H01L21/336

CPC分类号： H01L27/0266

摘要： An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.

摘要翻译： 一种用于提供静电放电保护的集成电路，其包括接触焊盘，包括具有衬底的晶体管的CMOS器件和用于提供耦合在所述接触焊盘和所述CMOS器件之间的静电放电保护的CDM钳位，所述CDM夹具包括至少一个 有源器件，其中CDM钳位将积聚在晶体管的衬底中的静电电荷传导到接触焊盘，并且其中CMOS器件耦合在高压线和低电压线之间。

公开(公告)号：US07253999B2

公开(公告)日：2007-08-07

申请号：US10446049

申请日：2003-05-28

申请人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H01L27/0248 ,  H03K17/0822

摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

摘要翻译： 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。