公开(公告)号：US5481122A

公开(公告)日：1996-01-02

申请号：US279874

申请日：1994-07-25

申请人： Ming-Jiunn Jou ,  Chuan-Ming Chang ,  Biing-Jye Lee ,  Jyh-Feng Lin

发明人： Ming-Jiunn Jou ,  Chuan-Ming Chang ,  Biing-Jye Lee ,  Jyh-Feng Lin

IPC分类号： H01L33/02 ,  H01L33/30 ,  H01L33/42 ,  H01L33/00

CPC分类号： H01L33/30 ,  H01L33/42 ,  H01L33/02

摘要： A surface emitting AlGaInP LED having an ITO layer as a window layer to eliminate the current crowding effect, and an ohmic contact layer between its double hetero-structure of AlGaInP and the ITO layer, so that ITO can be utilized with the double hetero-structure of AlGaInP.

摘要翻译： 具有ITO层作为窗口层的表面发射AlGaInP LED，以消除电流拥挤效应，以及AlGaInP的双异质结构与ITO层之间的欧姆接触层，使得可以利用双异质结构 的AlGaInP。

公开(公告)号：USRE35665E

公开(公告)日：1997-11-18

申请号：US668601

申请日：1996-06-25

申请人： Jyh-Feng Lin ,  Chuan-Ming Chang ,  Biing-Jye Lee ,  Ming-Jiunn Jou

发明人： Jyh-Feng Lin ,  Chuan-Ming Chang ,  Biing-Jye Lee ,  Ming-Jiunn Jou

IPC分类号： H01L33/02 ,  H01L33/30 ,  H01L33/42 ,  H01L33/00

CPC分类号： H01L33/30 ,  H01L33/42 ,  H01L33/02

摘要： A surface emitting AlGaInP LED having an ITO layer as a window layer to eliminate the current crowding effect, and an ohmic contact layer between its double hereto-structure of AlGaInP and the ITO layer, so that ITO can be utilized with the double hereto-structure of AlGaInP.

摘要翻译： 具有ITO层作为窗口层的表面发射AlGaInP LED，以消除电流拥挤效应，以及在AlGaInP和ITO层的双重结构之间的欧姆接触层，使得可以利用双重结构 的AlGaInP。

公开(公告)号：US06238993B1

公开(公告)日：2001-05-29

申请号：US09300047

申请日：1999-04-27

申请人： Jyh-Feng Lin ,  Kwan-Jen Chu ,  Yi-Pin Shen ,  Jer-Yuan Sheu

发明人： Jyh-Feng Lin ,  Kwan-Jen Chu ,  Yi-Pin Shen ,  Jer-Yuan Sheu

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L27/1112

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness. A method is described for fabricating such novel polysilicon load resistors, which can be used for operating 4T SRAMs at temperatures, as low as −45C., while not appreciably adding to process or device complexity.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在亚微米，基于NMOS的4晶体管SRAM单元中减少低掺杂多晶硅负载电阻器的其它过量的负TCR的方法。 高负TCR的问题是，当在低温下工作时，工作电流下降太靠近器件泄漏电流时，可能会发生电池故障。 本发明的关键是新颖的PN结方法，其使多晶硅电阻在较冷的温度下变得更厚。 沿着多晶硅电阻器的整个长度形成垂直PN结，并且PN结的温度依赖空间电荷区域用于调制电阻器的有效电气厚度。 因此，热激活晶界传导与冷温度降低的不良趋势通过电阻器厚度的轻微同时增加来部分地补偿。 描述了一种用于制造这种新型多晶硅负载电阻器的方法，其可用于在低至-45℃的温度下操作4T SRAM，同时不显着地增加工艺或器件复杂性。

公开(公告)号：US5915178A

公开(公告)日：1999-06-22

申请号：US986531

申请日：1997-12-08

申请人： An-Min Chiang ,  Long-Shang Juang ,  Chi-Shiang Lee ,  Jyh-Feng Lin

发明人： An-Min Chiang ,  Long-Shang Juang ,  Chi-Shiang Lee ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

摘要： A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.

摘要翻译： 已经开发了用于制造闪速EEPROM装置的方法，其包括用于提高快速EEPROM装置的耐久性的浅重掺杂的源极侧区域。 该方法在创建控制栅极结构之前，在与半导体衬底中相邻的浮栅结构的一侧放置浅的离子注入的砷区。 添加浅离子注入的砷区域可以提高源极耦合比，从而与快速EEPROM器件相比，快速EEPROM器件能够维持大约1,000,000个编程/擦除周期，与没有浅源的器件相比， 侧面区域，只能维持大约40万个编程/擦除周期。

公开(公告)号：US5895240A

公开(公告)日：1999-04-20

申请号：US884916

申请日：1997-06-30

申请人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

发明人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

摘要翻译： 本发明提供一种形成用于半导体存储器件的阶梯状沟槽氧化物结构的结构和方法。 阶梯状沟槽氧化物结构在围绕隧道氧化物层30的栅极氧化物20中具有“氧化物步骤”（例如，252或34A，34B，34C）。形成氧化物步骤34，其中氧化物稀化效应通常使隧道氧化物30沉降 围绕隧道氧化物层30的周边。氧化物步骤34 252补偿氧化物稀化效应并消除与氧化物稀化效应相关的问题。 氧化物步骤优选使用一个光掩模形成，以使用不同的光致抗蚀剂曝光时间形成两个不同尺寸的开口。 优选的方法包括在第一（栅极）氧化物层220中形成第一隧道开口220A。然后，在所述暴露的衬底和所述第一氧化物层220上形成第二氧化物层250.第二开口250A（小于第一开口） 形成在第二氧化物层中，从而形成第一步骤252.接下来，在所述暴露的基板上形成第三氧化物层270，第一氧化物层220和第二氧化物层250由此传播第一步骤252.氧化物变薄边缘 效果通过第一步消除。

公开(公告)号：US06613592B1

公开(公告)日：2003-09-02

申请号：US10132358

申请日：2002-04-25

申请人： Shin-Kai Chen ,  Chun-Chen Yeh ,  Jyh-Feng Lin

发明人： Shin-Kai Chen ,  Chun-Chen Yeh ,  Jyh-Feng Lin

IPC分类号： H01L2100

CPC分类号： H01L22/00 ,  H01L22/34

摘要： A new method is provided to monitor and to prevent IMD oxide irregularities such as IMD oxide cracks. A monitoring pattern is inserted in the test line of the fabrication substrate to monitor the strength of the created layer of IMD oxide. Variations in the characteristics of the created layer of IMD oxide can in this manner be detected. In addition, design rules are provided that are aimed at avoiding layers of IMD oxide that have proven or are known to be particularly prone to the occurrence of IMD oxide cracks.

摘要翻译： 提供了一种新的方法来监测和防止IMD氧化物不规则性，如IMD氧化物裂​​纹。 在制造衬底的测试线中插入监测图案，以监测所产生的IMD氧化物层的强度。 可以以这种方式检测所形成的IMD氧化物层的特性的变化。 此外，提供了旨在避免已经证明或已知特别容易发生IMD氧化物裂​​纹的IMD氧化物层的设计规则。

公开(公告)号：US06369428B2

公开(公告)日：2002-04-09

申请号：US09804390

申请日：2001-03-13

申请人： Jyh-Feng Lin ,  Kwan-Jen Chu ,  Yi-Pin Shen ,  Jer-Yuan Sheu

发明人： Jyh-Feng Lin ,  Kwan-Jen Chu ,  Yi-Pin Shen ,  Jer-Yuan Sheu

IPC分类号： H01L2362

CPC分类号： H01L28/20 ,  H01L27/1112

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness. A method is described for fabricating such novel polysilicon load resistors, which can be used for operating 4T SRAMs at temperatures, as low as −45 C., while not appreciably adding to process or device complexity.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及用于减小亚微米，基于NMOS的4晶体管SRAM单元中的低掺杂多晶硅负载电阻器的其它过量的负TCR的方法。 高负TCR的问题是，当在低温下工作时，工作电流下降太靠近器件泄漏电流时，可能会发生电池故障。 本发明的关键是新颖的PN结方法，其使多晶硅电阻在较冷的温度下变得更厚。 沿着多晶硅电阻器的整个长度形成垂直PN结，并且PN结的温度依赖空间电荷区域用于调制电阻器的有效电气厚度。 因此，热激活晶界传导与冷温度降低的不良趋势通过电阻器厚度的轻微同时增加来部分地补偿。 描述了一种用于制造这种新型多晶硅负载电阻器的方法，其可用于在低至-45℃的温度下操作4T SRAM，同时不显着地增加工艺或器件复杂性。

公开(公告)号：US6040223A

公开(公告)日：2000-03-21

申请号：US373636

申请日：1999-08-13

申请人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

发明人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si.sub.3 N.sub.4 extending over the portion of the trapezoidal-shaped SiO.sub.2 layer that forms part of the composite sidewall spacer protects the SiO.sub.2 from etching. This results in more reliable contacts without degrading the FET performance.

摘要翻译： 实现了具有复合侧壁间隔物的改进的多晶硅FET栅电极的方法。 在基板上形成多晶硅栅电极之后，沉积具有梯形形状的SiO 2应力释放层。 沉积Si 3 N 4层并使用SiO 2层等离子体蚀刻回蚀刻端点检测层，以形成包括梯形氧化物层的部分的复合侧壁间隔物。 SiO 2层保护源极/漏极区域免受可能导致高漏电流的等离子体蚀刻损伤。 Si 3 N 4也在多晶硅栅电极的上边缘处在SiO 2层上延伸。 当使用氢氟酸湿蚀刻从剩余的氧化物从源极/漏极区域移除时，这防止了沿着栅电极的SiO 2的侵蚀。 当绝缘层沉积在FET上方，并且自对准接触开口被蚀刻到源极/漏极区域并且在栅电极上延伸时，Si3N4延伸超过形成复合材料的一部分的梯形SiO 2层的部分 侧壁间隔件保护SiO 2免受蚀刻。 这导致更可靠的触点，而不会降低FET性能。

公开(公告)号：US5956566A

公开(公告)日：1999-09-21

申请号：US213454

申请日：1998-12-17

申请人： Jyh-Feng Lin ,  Hon-Hung Lui ,  Yi-Te Chen

发明人： Jyh-Feng Lin ,  Hon-Hung Lui ,  Yi-Te Chen

IPC分类号： H01L23/544 ,  G01R27/14 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： A method and test site for monitoring the extent of buried contact trench formation in MOS FET integrated circuit wafers is described. A number of doped silicon parallel first test electrodes are formed in test site regions of a wafer and connected in series. The test site regions are located in the spaces between chip regions of the wafer. A layer of gate oxide is then deposited over the wafer. Test openings over the first test electrodes and buried contact openings are etched in the gate oxide layer at the same time. The test openings have the same size and shape as the buried contact openings. After polysilicon and metal silicide is deposited a photoresist mask is formed to etch the buried contact electrodes, the gate electrodes, and second test electrodes which are located directly above the test openings. Any misalignment in the photoresist mask will cause trenches to be formed in the first test electrodes as well as the formation of buried contact trenches. These trenches in the first test electrodes will cause an increase the resistance of the first test electrodes which is related to the extent of the buried contact trenches. The first test electrodes can be oriented to measure the extent of buried contact trench formation regardless of orientation.

摘要翻译： 描述了用于监测MOS FET集成电路晶片中的埋入接触沟槽形成程度的方法和测试部位。 多个掺杂的硅平行的第一测试电极形成在晶片的测试位置区域并串联连接。 测试位置区域位于晶片的芯片区域之间的空间中。 然后在晶片上沉积一层栅极氧化物。 在第一测试电极和埋入的接触开口上的测试开口同时在栅极氧化物层中被蚀刻。 测试开口具有与埋入的接触开口相同的尺寸和形状。 在沉积多晶硅和金属硅化物之后，形成光致抗蚀剂掩模以蚀刻位于测试开口正上方的掩埋接触电极，栅电极和第二测试电极。 光致抗蚀剂掩模中的任何未对准将导致在第一测试电极中形成沟槽以及形成埋入的接触沟槽。 第一测试电极中的这些沟槽将引起第一测试电极的电阻增加，其与埋入的接触沟槽的程度相关。 第一测试电极可以被定向以测量埋入接触沟槽形成的程度，而不管取向如何。

公开(公告)号：US5917215A

公开(公告)日：1999-06-29

申请号：US148555

申请日：1998-09-04

申请人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

发明人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

摘要翻译： 本发明提供一种形成用于半导体存储器件的阶梯状沟槽氧化物结构的结构和方法。 阶梯状沟槽氧化物结构在围绕隧道氧化物层30的栅极氧化物20中具有“氧化物步骤”（例如，252或34A，34B，34C）。形成氧化物步骤34，其中氧化物稀化效应通常使隧道氧化物30沉降 围绕隧道氧化物层30的周边。氧化物步骤34 252补偿氧化物稀化效应并消除与氧化物稀化效应相关的问题。 氧化物步骤优选使用一个光掩模形成，以使用不同的光致抗蚀剂曝光时间形成两个不同尺寸的开口。 优选的方法包括在第一（栅极）氧化物层220中形成第一隧道开口220A。然后，在所述暴露的衬底和所述第一氧化物层220上形成第二氧化物层250.第二开口250A（小于第一开口） 形成在第二氧化物层中，从而形成第一步骤252.接下来，在所述暴露的基板上形成第三氧化物层270，第一氧化物层220和第二氧化物层250由此传播第一步骤252.氧化物变薄边缘 效果通过第一步消除。