公开(公告)号：US5956566A

公开(公告)日：1999-09-21

申请号：US213454

申请日：1998-12-17

申请人： Jyh-Feng Lin ,  Hon-Hung Lui ,  Yi-Te Chen

发明人： Jyh-Feng Lin ,  Hon-Hung Lui ,  Yi-Te Chen

IPC分类号： H01L23/544 ,  G01R27/14 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： A method and test site for monitoring the extent of buried contact trench formation in MOS FET integrated circuit wafers is described. A number of doped silicon parallel first test electrodes are formed in test site regions of a wafer and connected in series. The test site regions are located in the spaces between chip regions of the wafer. A layer of gate oxide is then deposited over the wafer. Test openings over the first test electrodes and buried contact openings are etched in the gate oxide layer at the same time. The test openings have the same size and shape as the buried contact openings. After polysilicon and metal silicide is deposited a photoresist mask is formed to etch the buried contact electrodes, the gate electrodes, and second test electrodes which are located directly above the test openings. Any misalignment in the photoresist mask will cause trenches to be formed in the first test electrodes as well as the formation of buried contact trenches. These trenches in the first test electrodes will cause an increase the resistance of the first test electrodes which is related to the extent of the buried contact trenches. The first test electrodes can be oriented to measure the extent of buried contact trench formation regardless of orientation.

摘要翻译： 描述了用于监测MOS FET集成电路晶片中的埋入接触沟槽形成程度的方法和测试部位。 多个掺杂的硅平行的第一测试电极形成在晶片的测试位置区域并串联连接。 测试位置区域位于晶片的芯片区域之间的空间中。 然后在晶片上沉积一层栅极氧化物。 在第一测试电极和埋入的接触开口上的测试开口同时在栅极氧化物层中被蚀刻。 测试开口具有与埋入的接触开口相同的尺寸和形状。 在沉积多晶硅和金属硅化物之后，形成光致抗蚀剂掩模以蚀刻位于测试开口正上方的掩埋接触电极，栅电极和第二测试电极。 光致抗蚀剂掩模中的任何未对准将导致在第一测试电极中形成沟槽以及形成埋入的接触沟槽。 第一测试电极中的这些沟槽将引起第一测试电极的电阻增加，其与埋入的接触沟槽的程度相关。 第一测试电极可以被定向以测量埋入接触沟槽形成的程度，而不管取向如何。

公开(公告)号：US6153517A

公开(公告)日：2000-11-28

申请号：US266880

申请日：1999-03-12

申请人： Kun-Jung Chuang ,  Shou-Yi Hsu ,  Yi-Te Chen ,  Hon-Hung Lui

发明人： Kun-Jung Chuang ,  Shou-Yi Hsu ,  Yi-Te Chen ,  Hon-Hung Lui

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L21/76855 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L23/485 ,  H01L2924/0002

摘要： A method is disclosed for forming a low resistance poly landing pad which is achieved by shunting the polysilicon of a landing pad with metallic conductors. A window is opened through a first dielectric layer to expose a conducting region over a semiconductor substrate. A metallic layer, deposited overall, is followed by an overall deposition of a polysilicon layer, with the layers being sufficient to fill the window completely. Metal and polysilicon outside the window is removed by chemical/mechanical polishing which also provides global planarization. Salicidation provides a silicide cover over the exposed surface of polysilicon, which was formed by the polishing. A second dielectric is deposited and an opening is formed to the landing pad. Electrical contact is made between metallization on the second dielectric layer and the salicide of the landing pad either, directly by simultaneous deposition of the metallization on the dielectric and the landing pad, or, by first forming a plug in the opening and then depositing the metallization.

摘要翻译： 公开了一种用于形成低电阻多接地焊盘的方法，其通过用金属导体分流着陆焊盘的多晶硅来实现。 通过第一电介质层打开窗口以暴露半导体衬底上的导电区域。 整个沉积的金属层之后是多晶硅层的总体沉积，其中层足以完全填充窗口。 通过化学/机械抛光除去窗户外的金属和多晶硅，还提供全局平面化。 Salicidation在多晶硅的暴露表面上提供硅化物覆盖层，其通过抛光形成。 沉积第二电介质并且对着陆焊盘形成开口。 在第二电介质层上的金属化和着陆焊盘的自对准硅化物之间进行电接触，直接通过金属化同时沉积在电介质和着陆焊盘上，或者首先在开口中形成插塞，然后沉积金属化 。

公开(公告)号：US5869370A

公开(公告)日：1999-02-09

申请号：US998631

申请日：1997-12-29

申请人： Kun-Jung Chuang ,  Hon-Hung Lui ,  Yi-Te Chen

发明人： Kun-Jung Chuang ,  Hon-Hung Lui ,  Yi-Te Chen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L21/8247 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/66825

摘要： A new method of forming a tunneling oxide film having a uniform thickness in the fabrication of a Flash EEPROM memory cell is described. A first oxide layer is provided on the surface of a semiconductor substrate wherein a portion of the first oxide layer is removed to expose the semiconductor substrate wherein the exposed portion of the semiconductor substrate comprises a tunneling window. A second oxide layer is deposited within the tunneling window. Thereafter, a thermal oxide layer is grown underlying the first oxide layer and the second oxide layer within the tunneling area wherein the presence of the second oxide layer provides for a uniform thermal oxide thickness throughout the tunneling window and wherein the second oxide layer and the thermal oxide layer together within the tunneling window form the tunneling oxide film in the fabrication of a memory cell.

摘要翻译： 描述了在制造闪存EEPROM存储单元中形成具有均匀厚度的隧道氧化物膜的新方法。 第一氧化物层设置在半导体衬底的表面上，其中去除第一氧化物层的一部分以露出半导体衬底，其中半导体衬底的暴露部分包括隧道窗。 第二氧化物层沉积在隧道窗内。 此后，在隧道区域内的第一氧化物层和第二氧化物层下方生长热氧化物层，其中第二氧化物层的存在在整个隧道窗口中提供均匀的热氧化物厚度，并且其中第二氧化物层和热 一起在隧道窗内的氧化物层在制造存储器单元中形成隧穿氧化膜。

公开(公告)号：USD683011S1

公开(公告)日：2013-05-21

申请号：US29400184

申请日：2011-08-24

申请人： Yi-Te Chen

设计人： Yi-Te Chen

公开(公告)号：USD683440S1

公开(公告)日：2013-05-28

申请号：US29400168

申请日：2011-08-24

申请人： Yi-Te Chen

设计人： Yi-Te Chen

公开(公告)号：USD683010S1

公开(公告)日：2013-05-21

申请号：US29400179

申请日：2011-08-24

申请人： Yi-Te Chen

设计人： Yi-Te Chen

公开(公告)号：US20060246615A1

公开(公告)日：2006-11-02

申请号：US11115285

申请日：2005-04-27

申请人： Wei Chang ,  Yi-Te Chen

发明人： Wei Chang ,  Yi-Te Chen

IPC分类号： H01L21/00

CPC分类号： H01S5/02244 ,  H01L24/97 ,  H01L33/483 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01S5/02276 ,  H01S5/183 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a vertical cavity surface emitting laser is disclosed. The method comprises the steps of: 1. punching one pin of each of a plurality of pin groups mounted on a frame for forming a large-area expanded surface on the pin; 2. coupling a plurality of vertical cavity surface emitting laser diodes to the expanded surfaces of the pins; 3. bonding the vertical cavity surface emitting laser diodes to the other pins by conducting wires; 4. holding the frame on which the vertical cavity surface emitting laser diodes are mounted by a plurality of housings having openings, notches, and mounting chambers to complete the assembly of the vertical cavity surface emitting laser diodes; and 5. cutting off connected portions among the pins to obtain the vertical cavity surface emitting lasers.

摘要翻译： 公开了制造垂直腔表面发射激光器的方法。 该方法包括以下步骤：1.对安装在框架上的多个销组中的每一个销进行冲压，以在销上形成大面积膨胀表面; 将多个垂直腔表面发射激光二极管耦合到销的扩展表面; 3.通过导线将垂直腔表面发射激光二极管与另一个引脚接合; 通过具有开口，凹口和安装室的多个壳体保持其上安装有垂直腔表面发射激光二极管的框架，以完成垂直腔表面发射激光二极管的组装; 并切断销之间的连接部分以获得垂直腔表面发射激光。

公开(公告)号：US20060246616A1

公开(公告)日：2006-11-02

申请号：US11115318

申请日：2005-04-27

申请人： Wei Chang ,  Yi-Te Chen

发明人： Wei Chang ,  Yi-Te Chen

IPC分类号： H01L21/00

CPC分类号： H01S5/02244 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01S5/02212 ,  H01S5/0683 ,  H01L2924/00014

摘要： A laser diode and a manufacture method thereof are disclosed. The method of manufacturing the laser diode comprises the steps of: 1. coupling a photo diode chip with one of a plurality of pins on a frame; 2. coupling and overlapping a laser diode chip with the photo diode chip; 3. bonding the laser diode chip and the photo diode chip to the other pins on the frame by use of conducting wires; 4. using a housing having an opening, a notch, and a mounting chamber for holding the pins to complete the assembly of the laser diode; and 5. cutting off connected portions among the pins to obtain the laser diode. Be means of the simplified manufacture process, the laser diode is suitable for mass production and the production cost is substantially reduced.

摘要翻译： 公开了一种激光二极管及其制造方法。 制造激光二极管的方法包括以下步骤：1.将光电二极管芯片与框架上的多个引脚之一耦合; 激光二极管芯片与光电二极管芯片的耦合和重叠; 3.通过使用导线将激光二极管芯片和光电二极管芯片连接到框架上的其他引脚; 4.使用具有开口的壳体，凹口和用于保持所述销以完成所述激光二极管的组装的安装室; 并切断引脚之间的连接部分以获得激光二极管。 作为简化制造工艺的手段，激光二极管适合批量生产，生产成本大大降低。