公开(公告)号：US08860181B2

公开(公告)日：2014-10-14

申请号：US13413669

申请日：2012-03-07

申请人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

发明人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5228 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

摘要翻译： 薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部 底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在 底部ILD和顶部ILD。

公开(公告)号：US08575034B2

公开(公告)日：2013-11-05

申请号：US13283690

申请日：2011-10-28

申请人： Ming-Te Wei ,  Po-Chao Tsao ,  Ming-Tsung Chen

发明人： Ming-Te Wei ,  Po-Chao Tsao ,  Ming-Tsung Chen

IPC分类号： H01L21/461

CPC分类号： H01L21/28 ,  H01L21/823437 ,  H01L27/0207

摘要： The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.

摘要翻译： 半导体元件的制造方法技术领域本发明涉及半导体元件的制造方法。 首先，提供基板，并且在基板上形成具有第一宽度的第一布局结构。 然后，形成蚀刻掩模以覆盖第一布局结构，并且蚀刻掩模暴露第一布局结构的一部分。 之后，用蚀刻掩模蚀刻第一布局结构以形成具有第二宽度的第二布局结构。 第二宽度小于第一宽度。 该制造方法能够完成两个不同方向的栅极结构的制造。 因此，布局灵活性得到改善。

公开(公告)号：US20130234292A1

公开(公告)日：2013-09-12

申请号：US13413669

申请日：2012-03-07

申请人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

发明人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

IPC分类号： H01L29/02

CPC分类号： H01L23/5228 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

摘要翻译： 薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部 底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在 底部ILD和顶部ILD。

公开(公告)号：US20130109163A1

公开(公告)日：2013-05-02

申请号：US13283690

申请日：2011-10-28

申请人： Ming-Te WEI ,  Po-Chao Tsao ,  Ming-Tsung Chen

发明人： Ming-Te WEI ,  Po-Chao Tsao ,  Ming-Tsung Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/28 ,  H01L21/823437 ,  H01L27/0207

摘要： The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.

摘要翻译： 半导体元件的制造方法技术领域本发明涉及半导体元件的制造方法。 首先，提供基板，并且在基板上形成具有第一宽度的第一布局结构。 然后，形成蚀刻掩模以覆盖第一布局结构，并且蚀刻掩模暴露第一布局结构的一部分。 之后，用蚀刻掩模蚀刻第一布局结构以形成具有第二宽度的第二布局结构。 第二宽度小于第一宽度。 该制造方法能够完成两个不同方向的栅极结构的制造。 因此，布局灵活性得到改善。

公开(公告)号：US09136348B2

公开(公告)日：2015-09-15

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

摘要翻译： 半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层， 所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物 而不直接接触轻掺杂的漏极。

公开(公告)号：US20130234261A1

公开(公告)日：2013-09-12

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

公开(公告)号：US20100073671A1

公开(公告)日：2010-03-25

申请号：US12237404

申请日：2008-09-25

申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Po-Chao Tsao

发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Po-Chao Tsao

IPC分类号： G01N21/88

CPC分类号： G03F7/70658 ,  G03F7/70633 ,  G03F7/7065 ,  G03F9/7076 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection.

摘要翻译： 公开了一种缺陷检查方法。 第一种缺陷检查系统用于通过与晶片上的对准标记对准来进行第一缺陷检查，作为第一缺陷检查的参考点。 然后在晶片上进行制造工艺，并且通过使用第二类型缺陷检查系统来执行第二缺陷检查，以使晶片上的对准标记作为第二缺陷检查的参考点。

公开(公告)号：US07595234B2

公开(公告)日：2009-09-29

申请号：US11532100

申请日：2006-09-15

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US20070066041A1

公开(公告)日：2007-03-22

申请号：US11532100

申请日：2006-09-15

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US20070049014A1

公开(公告)日：2007-03-01

申请号：US11161990

申请日：2005-08-25

申请人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

发明人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process to form a retarded interface layer between the silicon layer and the gate and source/drain region; forming a metal layer on the silicon layer; and reacting the metal layer with the silicon layer for forming a silicide layer.

摘要翻译： 一种在MOS晶体管上执行自对准硅化物工艺的方法，其中所述MOS晶体管包括栅极结构和源极/漏极区域，所述方法包括：执行选择性生长工艺以在所述栅极的顶部上形成硅层，并且所述源/ 漏区; 执行离子注入工艺以在硅层和栅极和源极/漏极区之间形成延迟界面层; 在所述硅层上形成金属层; 并使金属层与用于形成硅化物层的硅层反应。