公开(公告)号：US07704878B2

公开(公告)日：2010-04-27

申请号：US11240468

申请日：2005-10-03

申请人： Minh Van Ngo ,  Angela T. Hui ,  Amol Ramesh Joshi ,  Wenmei Li ,  Ning Cheng ,  Ankur Bhushan Agarwal ,  Norimitsu Takagi

发明人： Minh Van Ngo ,  Angela T. Hui ,  Amol Ramesh Joshi ,  Wenmei Li ,  Ning Cheng ,  Ankur Bhushan Agarwal ,  Norimitsu Takagi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76831

摘要： A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.

摘要翻译： 半导体器件中的接触结构包括介电材料层和通过介电材料形成的通孔。 接触结构还包括通过使用原子层沉积（ALD）和沉积在通孔中的金属在通孔的侧壁上形成的间隔物。

公开(公告)号：US08564041B2

公开(公告)日：2013-10-22

申请号：US11551532

申请日：2006-10-20

申请人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

发明人： Angela T. Hui ,  Wenmei Li ,  Minh Van Ngo ,  Amol Ramesh Joshi ,  Kuo-Tung Chang

IPC分类号： H01L27/108

CPC分类号： H01L29/78 ,  H01L27/115 ,  H01L27/11568

摘要： A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

摘要翻译： 存储器件包括多个存储单元和形成在存储单元上的电介质层。 存储器件还包括形成在电介质层中的触点和邻近触头的侧表面形成的间隔件。 间隔物可以抑制来自接触件的泄漏电流。

公开(公告)号：US07705390B2

公开(公告)日：2010-04-27

申请号：US12054081

申请日：2008-03-24

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L21/76 ,  H01L21/792

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US20080169502A1

公开(公告)日：2008-07-17

申请号：US12054081

申请日：2008-03-24

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US07368347B2

公开(公告)日：2008-05-06

申请号：US11538404

申请日：2006-10-03

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US20080079062A1

公开(公告)日：2008-04-03

申请号：US11538404

申请日：2006-10-03

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

公开(公告)号：US20080142874A1

公开(公告)日：2008-06-19

申请号：US11611860

申请日：2006-12-16

申请人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Hidehiko Shiraiwa ,  Takayuki Maruyama ,  Kuo-Tung Chang ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Harpreet Sachar ,  Simon Siu-Sing Chan

发明人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Hidehiko Shiraiwa ,  Takayuki Maruyama ,  Kuo-Tung Chang ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Harpreet Sachar ,  Simon Siu-Sing Chan

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L29/792 ,  H01L29/66833

摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.

摘要翻译： 提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

公开(公告)号：US20080023751A1

公开(公告)日：2008-01-31

申请号：US11461131

申请日：2006-07-31

申请人： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

发明人： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/115 ,  H01L29/66833

摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

摘要翻译： 一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

公开(公告)号：US08143661B2

公开(公告)日：2012-03-27

申请号：US11539984

申请日：2006-10-10

申请人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

发明人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11568

摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

摘要翻译： 提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。