公开(公告)号：US07705390B2

公开(公告)日：2010-04-27

申请号：US12054081

申请日：2008-03-24

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L21/76 ,  H01L21/792

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US20080169502A1

公开(公告)日：2008-07-17

申请号：US12054081

申请日：2008-03-24

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US07368347B2

公开(公告)日：2008-05-06

申请号：US11538404

申请日：2006-10-03

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

摘要翻译： 提供了制造双位闪存器件的方法。 方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。 提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。 侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。 去除第一多晶硅层的一部分和电荷俘获层的第一部分。 第一绝缘层共形沉积在绝缘构件和衬底上。 在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。 去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。 将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

公开(公告)号：US20080079062A1

公开(公告)日：2008-04-03

申请号：US11538404

申请日：2006-10-03

申请人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

发明人： Amol Ramesh Joshi ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L29/7923

摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

公开(公告)号：US07704878B2

公开(公告)日：2010-04-27

申请号：US11240468

申请日：2005-10-03

申请人： Minh Van Ngo ,  Angela T. Hui ,  Amol Ramesh Joshi ,  Wenmei Li ,  Ning Cheng ,  Ankur Bhushan Agarwal ,  Norimitsu Takagi

发明人： Minh Van Ngo ,  Angela T. Hui ,  Amol Ramesh Joshi ,  Wenmei Li ,  Ning Cheng ,  Ankur Bhushan Agarwal ,  Norimitsu Takagi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76831

摘要： A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.

摘要翻译： 半导体器件中的接触结构包括介电材料层和通过介电材料形成的通孔。 接触结构还包括通过使用原子层沉积（ALD）和沉积在通孔中的金属在通孔的侧壁上形成的间隔物。

公开(公告)号：US20090039405A1

公开(公告)日：2009-02-12

申请号：US11835542

申请日：2007-08-08

申请人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US20110278660A1

公开(公告)日：2011-11-17

申请号：US13190565

申请日：2011-07-26

申请人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US07829936B2

公开(公告)日：2010-11-09

申请号：US11873822

申请日：2007-10-17

申请人： Minghao Shen ,  Shenqing Fang ,  Wai Lo ,  Christie R. K. Marrian ,  Chungho Lee ,  Ning Cheng ,  Fred Cheung ,  Huaqiang Wu

发明人： Minghao Shen ,  Shenqing Fang ,  Wai Lo ,  Christie R. K. Marrian ,  Chungho Lee ,  Ning Cheng ,  Fred Cheung ,  Huaqiang Wu

IPC分类号： H01L21/331

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344

摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

摘要翻译： 提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。 这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。 通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。 此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个 拆分次光刻电荷存储节点。

公开(公告)号：US07732281B1

公开(公告)日：2010-06-08

申请号：US11410695

申请日：2006-04-24

申请人： Minghao Shen ,  Fred Cheung ,  Ning Cheng ,  Wei Zheng ,  Hiroyuki Kinoshita ,  Chih-Yuh Yang

发明人： Minghao Shen ,  Fred Cheung ,  Ning Cheng ,  Wei Zheng ,  Hiroyuki Kinoshita ,  Chih-Yuh Yang

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/7923

摘要： Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

摘要翻译： 提供了制造双位存储器件的方法。 在本发明的示例性实施例中，一种用于制造双位存储器件的方法包括形成覆盖衬底的电荷俘获层，并蚀刻穿过电荷俘获层的隔离开口。 在电荷俘获层之上和隔离开口内形成氧化物层。 制造控制栅极覆盖隔离开口和邻近隔离开口的电荷捕获层的部分。 使用控制栅极作为蚀刻掩模蚀刻氧化物层和电荷俘获层，并且使用控制栅极作为注入掩模将杂质掺杂剂注入到衬底中。

公开(公告)号：US07687360B2

公开(公告)日：2010-03-30

申请号：US11615365

申请日：2006-12-22

申请人： Hiroyuki Kinoshita ,  Ning Cheng ,  Minghao Shen

发明人： Hiroyuki Kinoshita ,  Ning Cheng ,  Minghao Shen

IPC分类号： H01L21/336

CPC分类号： H01L27/11563 ,  H01L27/115 ,  H01L27/11568

摘要： Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

摘要翻译： 提供了用于制造存储器件的方法。 一种方法包括制造覆盖在硅衬底上的电荷俘获堆叠，并在电荷俘获堆叠之间形成衬底中的位线区域。 绝缘元件形成在堆叠之间的位线区域之上。 电荷俘获堆被蚀刻以形成两个互补电荷存储节点并暴露硅衬底的部分。 硅通过选择性外延生长在暴露的硅衬底上生长并被氧化。 形成覆盖互补电荷存储节点和氧化的外延生长硅的控制栅层。