公开(公告)号：US06613657B1

公开(公告)日：2003-09-02

申请号：US10231133

申请日：2002-08-30

申请人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.

摘要翻译： 通过沉积BPSG，SA-CVD氧化物衬垫并将其流入底切区域，随后用P掺杂的HDP氧化物层填充间隙来补救由间隔物底切造成的器件泄漏。 实施方案包括在紧密间隔开的非易失性晶体管上沉积厚度为1,000至1,800的含有4至6重量％硼的BPSG，SA-CVD氧化物衬垫，并在沉积期间或之后加热以使BPSG流动， SA-CVD氧化物衬垫进入栅堆叠的侧壁间隔物的底切区域。 然后通过沉积厚度为6,000至10,000的P掺杂HDP层完成间隙填充。

公开(公告)号：US06809402B1

公开(公告)日：2004-10-26

申请号：US10217403

申请日：2002-08-14

申请人： Dawn Hopper ,  Minh Van Ngo ,  Atul Gupta ,  Tyagamohan Gottipati ,  John Caffall

发明人： Dawn Hopper ,  Minh Van Ngo ,  Atul Gupta ,  Tyagamohan Gottipati ,  John Caffall

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L27/115

摘要： Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

摘要翻译： 通过沉积能够流入底切区域的B掺杂的HDP或掺有BP的HDP氧化物间隙填充层来补救由间隔物底切造成的器件泄漏。 实施例包括沉积含有4至6重量％的B或BP掺杂的HDP氧化物膜。 ％B超过紧密间隔开的非挥发性晶体管，并且在沉积期间和之后加热，以使B-或BP-HDP氧化物完全流入并填充侧壁间隔物上的底切区域并致密化B或BP-HDP氧化物 。

公开(公告)号：US07118967B1

公开(公告)日：2006-10-10

申请号：US10368696

申请日：2003-02-19

申请人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

发明人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  H01L29/66833 ,  Y10S438/954

摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

摘要翻译： 一种保护电荷捕获电介质闪存单元免受UV感应充电的方法，包括在半导体器件中制造包括电荷捕获介电电荷存储层的电荷捕获电介质闪存单元; 并且在形成电荷捕获介电电荷存储层之后的处理步骤期间，保护电荷捕获电介质闪速存储器单元暴露于足以在电荷俘获电介质闪存单元中沉积不可擦除电荷的UV辐射水平。 在一个实施例中，保护步骤是通过选择不包括半导体器件的使用，产生或曝光到足以沉积不可擦除电荷的紫外线辐射的水平的BEOL制造中的工艺进行的。

公开(公告)号：US6093973A

公开(公告)日：2000-07-25

申请号：US163601

申请日：1998-09-30

申请人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

发明人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

IPC分类号： G03F7/09 ,  G03F7/11 ,  H01L23/544

CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S257/915

摘要： An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.

摘要翻译： 在深紫外光致抗蚀剂和抗反射涂层之间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。 实施方案包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

公开(公告)号：US06784095B1

公开(公告)日：2004-08-31

申请号：US10073066

申请日：2002-02-12

申请人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

发明人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

IPC分类号： H01L214767

CPC分类号： H01L21/76831 ,  H01L21/76826 ,  H01L21/76829

摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.

摘要翻译： 通过在其上形成阻挡层之前用磷化氢等离子体表面处理电介质层来形成改进的电介质层。 实施例包括在低k电介质层中形成沟槽，并通过对PECVD室中产生的磷化氢等离子体进行电介质修饰沟槽的侧表面。 通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积含铜层来形成导电特征。

公开(公告)号：US06723634B1

公开(公告)日：2004-04-20

申请号：US10097004

申请日：2002-03-14

申请人： Minh Van Ngo ,  Dawn Hopper

发明人： Minh Van Ngo ,  Dawn Hopper

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76855

摘要： Semiconductor devices comprising interconnects with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing, in N2 and H2, exposed surfaces of a dielectric layer defining an opening, and then depositing Ta to form a composite layer lining the opening. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing dielectric material, such as F-silicon oxide derived from F-TEOS, impinging a pulsed laser light beam on exposed surfaces of the F-silicon oxide defining the opening in a flow of N2 and H2, and then depositing Ta to form a composite barrier layer comprising graded tantalum nitride and &agr;-Ta lining the opening. Laser thermal annealing in N2 and H2 depletes the exposed silicon oxide surfaces of F while enriching the surfaces with N2. Deposited Ta reacts with the N2 in the N2-enriched surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon. Cu is then deposited, CMP conducted and a capping layer deposited to form the dual damascene structure.

摘要翻译： 通过在N2和H2中的激光热退火，限定开口的电介质层的暴露表面，然后沉积Ta以形成衬套开口的复合层，形成具有改善的阻挡层与电介质层的粘附性的互连的半导体器件。 实施例包括在包括含F的电介质材料的层间电介质中形成双镶嵌开口，例如衍生自F-TEOS的F-氧化硅，在脉冲激光束中冲击限定开口的F-氧化硅的暴露表面 N2和H2的流动，然后沉积Ta形成复合阻挡层，该复合势垒层包括在开口内衬的梯度氮化钽和α-Ta。 N2和H2中的激光热退火消耗了F的暴露的氧化硅表面，同时用N2富集表面。 沉积的Ta与富氮的表面区域中的N 2反应以形成包含氮化钽梯度层和其上的α-Ta层的复合势垒层。 然后沉积Cu，进行CMP并沉积覆盖层以形成双镶嵌结构。

公开(公告)号：US06642619B1

公开(公告)日：2003-11-04

申请号：US09614300

申请日：2000-07-12

申请人： Minh Van Ngo ,  Dawn Hopper ,  Jeremy Martin

发明人： Minh Van Ngo ,  Dawn Hopper ,  Jeremy Martin

IPC分类号： H01L2348

CPC分类号： H01L21/76844 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Fluorine doped Silicon Oxide (SiO2)/Tantalum interface and method for manufacturing the same are provided that ensure the structural integrity of integrated circuits that include a Fluorine doped Silicon Oxide structure and a corresponding Tantalum barrier layer. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface comprises an amount of Silicon Nitride (SiN) in a surface region of a Fluorine doped Silicon Oxide structure. The concentration of Fluorine in the surface region is depleted with respect to a concentration of Fluorine in the remaining portion(s) of the Fluorine doped Silicon Oxide structure. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface also includes an amount of Tantalum Nitride (TaN) in the surface region. Finally, a Tantalum barrier layer is deposited over the surface region.

摘要翻译： 提供氟掺杂的氧化硅（SiO 2）/钽界面及其制造方法，其确保包括氟掺杂的氧化硅结构和相应的钽阻挡层的集成电路的结构完整性。 氟掺杂的氧化硅（SiO 2）/钽界面在氟掺杂的氧化硅结构的表面区域中包含一定量的氮化硅（SiN）。 相对于氟掺杂氧化硅结构的剩余部分中氟的浓度，表面区域中氟的浓度被耗尽。 氟掺杂的氧化硅（SiO 2）/钽界面还包括在表面区域中的一定量的氮化钽（TaN）。 最后，在表面区域上沉积有钽阻挡层。

公开(公告)号：US07070911B1

公开(公告)日：2006-07-04

申请号：US10350472

申请日：2003-01-23

申请人： Dawn Hopper ,  Kouros Ghandehari ,  Minh Van Ngo

发明人： Dawn Hopper ,  Kouros Ghandehari ,  Minh Van Ngo

IPC分类号： G03F7/00

CPC分类号： G03F7/091 ,  Y10S430/151

摘要： A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.

摘要翻译： 提出了一种用于在制造半导体期间降低光致抗蚀剂中的驻波的结构和方法。 本发明的实施例包括一种在制造半导体器件期间减少光致抗蚀剂中的驻波形成的方法，包括沉积具有高于材料的消光系数的第一抗反射涂层，以及沉积具有高于上述消光系数的第二抗反射涂层 第一抗反射涂层，使得第一抗反射涂层和第二抗反射涂层在光刻工艺期间减少光致抗蚀剂中驻波的形成。

公开(公告)号：US06900121B1

公开(公告)日：2005-05-31

申请号：US10097015

申请日：2002-03-14

申请人： Minh Van Ngo ,  Arvind Halliyal ,  Dawn Hopper

发明人： Minh Van Ngo ,  Arvind Halliyal ,  Dawn Hopper

IPC分类号： H01L21/3105 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/3105 ,  H01L21/76819 ,  H01L27/115

摘要： Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.

摘要翻译： 通过激光热退火基本上减少了氧化物空隙。 实施例包括通过在间隔开的晶体管上沉积BPSG来制造闪速存储器件，作为第一层间电介质，其中形成在晶体管之间的间隙中的空隙，并且在流动的氮气中激发热退火BPSG层，以通过回流BPSG层来消除或基本上减少空隙。

公开(公告)号：US06686232B1

公开(公告)日：2004-02-03

申请号：US10173717

申请日：2002-06-19

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

IPC分类号： H01L21471

CPC分类号： H01L29/6659 ,  C23C16/345 ,  H01L21/3185 ,  H01L29/6656

摘要： A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.

摘要翻译： 通过减少NH 3流速和/或降低SiH 4流速，通过PECVD以超低沉积速率沉积薄的氮化硅层。 实施例包括在栅电极上的薄氧化硅衬垫上以100至800sccm的NH 3流速，50至100sccm的SiH 4流率和50至100sccm的SiH 4流速沉积例如100或更小的氮化硅薄层 0.8〜1.8乇减压。 本发明的实施例还包括在多个沉积阶段中沉积氮化硅层，例如，将氮化硅层沉积在各自的五个沉积阶段中。