公开(公告)号：US6093973A

公开(公告)日：2000-07-25

申请号：US163601

申请日：1998-09-30

申请人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

发明人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

IPC分类号： G03F7/09 ,  G03F7/11 ,  H01L23/544

CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S257/915

摘要： An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.

摘要翻译： 在深紫外光致抗蚀剂和抗反射涂层之间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。 实施方案包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

公开(公告)号：US06429141B1

公开(公告)日：2002-08-06

申请号：US09589105

申请日：2000-06-08

申请人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

发明人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

IPC分类号： H01L21461

CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S257/915

摘要： An oxide hard mask is formed during semiconductor device manufacturing between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include a method of manufacturing a semiconductor device comprising depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.

摘要翻译： 在深紫外光致抗蚀剂和抗反射涂层之间的半导体器件制造期间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。 实施例包括制造半导体器件的方法，包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

公开(公告)号：US06594024B1

公开(公告)日：2003-07-15

申请号：US09886863

申请日：2001-06-21

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Carmen Morales

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Carmen Morales

IPC分类号： G01B1128

CPC分类号： B24B37/005 ,  B24B49/12 ,  G01N21/47 ,  G01N21/9501 ,  H01L21/30625

摘要： One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.

摘要翻译： 本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统，以便确定包括晶片的CMP工艺端点，其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库，以确定晶片的状态。 另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法，其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。

公开(公告)号：US06597463B1

公开(公告)日：2003-07-22

申请号：US09880591

申请日：2001-06-13

申请人： Bhanwar Singh ,  Cristina Cheung ,  Jay Bhakta ,  Carmen Morales ,  Junwei Bao

发明人： Bhanwar Singh ,  Cristina Cheung ,  Jay Bhakta ,  Carmen Morales ,  Junwei Bao

IPC分类号： G01B1106

CPC分类号： G01B11/0641 ,  G01B11/0625

摘要： A system and method are disclosed for providing in-situ monitoring of an oxidized ARC layer disposed over an ARC layer. By monitoring the thickness of the oxidized portion of the ARC layer during semiconductor processing, one or more process control parameters may be adjusted to help achieve a desired oxidized portion thickness. As a result, the number of process steps required to achieve the desired oxidized portion thickness may be reduced, providing a more efficient and economical process

摘要翻译： 公开了用于提供设置在ARC层上的氧化ARC层的原位监测的系统和方法。 通过在半导体处理期间监测ARC层的氧化部分的厚度，可以调整一个或多个工艺控制参数以帮助实现所需的氧化部分厚度。 结果，可以减少实现所需氧化部分厚度所需的工艺步骤的数量，从而提供更有效和经济的工艺

公开(公告)号：US6165855A

公开(公告)日：2000-12-26

申请号：US205068

申请日：1998-12-04

申请人： Paul R. Besser ,  Bhanwar Singh ,  Darrell M. Erb ,  Susan H. Chen ,  Carmen Morales

发明人： Paul R. Besser ,  Bhanwar Singh ,  Darrell M. Erb ,  Susan H. Chen ,  Carmen Morales

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/7685 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/76885 ,  H01L2221/1078

摘要： An anti-reflective coating for use in microcircuit fabrication and specifically using ultraviolet photolithographic processes. A three layered anti-reflective coating is used to enhance metallization etching in the construction of microcircuits. The coating features a titanium nitride anti-reflective layer sandwiched between two titanium metal layers. The upper titanium layer protects subsequently applied deep ultraviolet photoresists from the deleterious effects of the titanium nitride anti-reflective layer. The unique character of the three layer anti-reflective coating allows the use of an efficient single chamber fabrication process to form the three layer coating.

摘要翻译： 用于微电路制造的抗反射涂层，特别是使用紫外光刻工艺。 三层抗反射涂层用于增强微电路结构中的金属化蚀刻。 该涂层具有夹在两个钛金属层之间的氮化钛抗反射层。 上钛层保护随后施加的深紫外光致抗蚀剂免受氮化钛抗反射层的有害影响。 三层抗反射涂层的独特特征允许使用有效的单室制造工艺来形成三层涂层。

公开(公告)号：US06459945B1

公开(公告)日：2002-10-01

申请号：US09311223

申请日：1999-05-13

申请人： Bhanwar Singh ,  Carmen Morales ,  Bharath Rangarajan

发明人： Bhanwar Singh ,  Carmen Morales ,  Bharath Rangarajan

IPC分类号： G06F1900

CPC分类号： B24B37/013 ,  B24B49/04 ,  H01L21/67253 ,  H01L22/34

摘要： The present invention relates to a test wafer for use in optimizing a process. The test wafer includes a substrate and a material layer formed over the substrate, wherein the material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. A spindle drive system is also provided for driving at least one spindle. One end of the at least one spindle is coupled to a polishing pad, which is employed in forming the test regions.

摘要翻译： 本发明涉及用于优化工艺的测试晶片。 测试晶片包括衬底和形成在衬底上的材料层，其中材料层包括N个测试区域（N是大于1的整数）。 测试区域中的至少一个具有与另一个测试区域不同的材料层厚度。 还提供用于驱动至少一个主轴的主轴驱动系统。 所述至少一个心轴的一端连接到用于形成所述测试区域的抛光垫。

公开(公告)号：US6066578A

公开(公告)日：2000-05-23

申请号：US980888

申请日：1997-12-01

申请人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

发明人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

IPC分类号： G03F7/16 ,  H01L21/027 ,  H01L21/311 ,  H01L21/312 ,  G03C5/00

CPC分类号： G03F7/16 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/0274 ,  H01L21/3124

摘要： A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

公开(公告)号：US07080330B1

公开(公告)日：2006-07-18

申请号：US10379738

申请日：2003-03-05

申请人： Bryan Choo ,  Bharath Rangarajan ,  Bhanwar Singh ,  Carmen Morales

发明人： Bryan Choo ,  Bharath Rangarajan ,  Bhanwar Singh ,  Carmen Morales

IPC分类号： G06F17/50

CPC分类号： G03F7/70633 ,  G01N21/4788 ,  G01N21/956 ,  G03F7/70625

摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

摘要翻译： 公开了用于监测和控制半导体制造工艺的系统和方法。 通过该过程形成的晶片上形成的一个或多个结构便于同时测量临界尺寸并通过散射测量法或扫描电子显微镜（SEM）覆盖。 同时测量可减轻制造效率低下，从而减少制造过程所需的时间和空间。 可以利用这些测量来产生反馈和/或前馈数据，以选择性地控制一个或多个制造部件和/或与之相关联的操作参数以实现所需的临界尺寸并减轻重叠误差。

公开(公告)号：US06515342B1

公开(公告)日：2003-02-04

申请号：US09557680

申请日：2000-04-25

申请人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

发明人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

IPC分类号： H01L2900

CPC分类号： G03F7/16 ,  H01L21/02134 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/0274 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3124

摘要： A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

摘要翻译： 公开了一种用于在低介电常数层中形成多个结构的系统和方法。 低介电常数层设置在半导体上。 所述方法和系统包括将低介电常数层暴露于改善光致抗蚀剂的粘附性的试剂，在低介电常数层上提供光致抗蚀剂层，图案化光致抗蚀剂，以及蚀刻低介电常数层以形成多个 结构。

公开(公告)号：US06383947B1

公开(公告)日：2002-05-07

申请号：US09703513

申请日：2000-10-31

申请人： Paul R. Besser ,  Bhanwar Singh ,  Darrell M. Erb ,  Susan H. Chen ,  Carmen Morales

发明人： Paul R. Besser ,  Bhanwar Singh ,  Darrell M. Erb ,  Susan H. Chen ,  Carmen Morales

IPC分类号： H01L2131

CPC分类号： H01L21/7685 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/76885 ,  H01L2221/1078

摘要： An anti-reflective coating for use in microcircuit fabrication and specifically using ultraviolet photolithographic processes. A three-layered anti-reflective coating is used to enhance metallization etching in the construction of microcircuits. The coating features a titanium nitride anti-reflective layer sandwiched between two titanium metal layers. The upper titanium layer protects subsequently applied deep ultraviolet photoresists from the deleterious effects of the titanium nitride anti-reflective layer. The unique character of the three layer anti-reflective coating allows the use of an efficient single chamber fabrication process to form the three-layer coating.

摘要翻译： 用于微电路制造的抗反射涂层，特别是使用紫外光刻工艺。 使用三层抗反射涂层来增强微电路结构中的金属化蚀刻。 该涂层具有夹在两个钛金属层之间的氮化钛抗反射层。 上钛层保护随后施加的深紫外光致抗蚀剂免受氮化钛抗反射层的有害影响。 三层抗反射涂层的独特特征允许使用有效的单室制造工艺来形成三层涂层。