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公开(公告)号：US20180248003A1
公开(公告)日：2018-08-30
申请号：US15755098
申请日：2015-12-28
IPC分类号： H01L29/08 , H01L29/739 , H01L29/861 , H01L29/868 , H01L21/225 , H01L21/04 , H01L29/06
CPC分类号： H01L29/083 , H01L21/041 , H01L21/0455 , H01L21/2253 , H01L21/2258 , H01L21/263 , H01L29/0619 , H01L29/0638 , H01L29/0688 , H01L29/0834 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/66128 , H01L29/66348 , H01L29/7397 , H01L29/78 , H01L29/861 , H01L29/8611 , H01L29/868
摘要： An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.
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公开(公告)号：US20210305174A1
公开(公告)日：2021-09-30
申请号：US17155016
申请日：2021-01-21
发明人： Akito NISHII , Tatsuo HARADA , Katsumi URYU , Noritsugu NOMURA , Sho TANAKA
IPC分类号： H01L23/00
摘要： According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w
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公开(公告)号：US20190109026A1
公开(公告)日：2019-04-11
申请号：US16055218
申请日：2018-08-06
发明人： Kinya YAMASHITA , Masaki UENO , Tatsuo HARADA , Noritsugu NOMURA
IPC分类号： H01L21/67 , H01L21/683
摘要： Provided is a technique for detaching a semiconductor chip from a mount tape without failures in the semiconductor chip, such as cracking and chipping. A semiconductor pick-up apparatus includes the following components: a pick-up stage above which a semiconductor chip is to be placed through a mount tape attached to the lower surface of the semiconductor chip; an expander holding and expanding the mount tape; a push-up needle projecting from the upper surface of the pick-up stage, and capable of pushing up the semiconductor chip through the mount tape; and a mechanism pushing up the push-up needle while operating the push-up needle so as to form a spiral shape.
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公开(公告)号：US20240295599A1
公开(公告)日：2024-09-05
申请号：US18414413
申请日：2024-01-16
发明人： Noritsugu NOMURA , Takuya YOSHIMURA
IPC分类号： G01R31/26
CPC分类号： G01R31/2601
摘要： Occurrence of partial discharge is reduce and the test of electrical properties of a semiconductor device is and stably performed. A semiconductor testing apparatus includes a stage, a probe, a separation section, and a gas supply section. The probe performs electrical input and output to and from the semiconductor device held on the stage. The separation section separates the space above the semiconductor device held on the stage into the pressurized space and the probe space including the probe. The gas supply section supplies gas to the pressurized space to pressurize the pressurized space.
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公开(公告)号：US20230351066A1
公开(公告)日：2023-11-02
申请号：US18059612
申请日：2022-11-29
发明人： Katsumi URYU , Koji OKUNO , Noritsugu NOMURA
IPC分类号： G06F30/12
CPC分类号： G06F30/12
摘要： A method for automatically arranging parts on a CAD comprises: part condition acquisition step A; part arrangement order acquisition step; boundary line acquisition step B; part arrangement step C; boundary line updating step; first repetition step; part type change step; and second repetition step. In step A, part boundary condition, set for each of types of parts, representing the type of the part to be permitted to be arranged adjacent to the part is acquired. In step B, boundary line boundary condition to be set for a boundary line parallel to an area termination end line of an arrangement area in X- or Y-direction is acquired. In step C, the part boundary condition set for the part and the boundary line boundary condition set for the boundary line arranged in the arrangement area are compared with each other, and the part is arranged when the conditions match each other.
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公开(公告)号：US20210098317A1
公开(公告)日：2021-04-01
申请号：US16874488
申请日：2020-05-14
发明人： Noritsugu NOMURA
摘要： When a voltage is applied to a semiconductor element formed into a semiconductor substrate for evaluating the electrical characteristic of the semiconductor element, partial discharge between the semiconductor element and an inter-element portion, adhesion of a foreign substance to the semiconductor substrate, and formation of a trace of a component in the semiconductor substrate are prevented. A semiconductor device includes a semiconductor substrate and a discharge inhibitor. The semiconductor substrate includes a plurality of semiconductor elements and an inter-element portion. The semiconductor elements are arranged in a spreading direction of the semiconductor substrate. The inter-element portion is between adjacent semiconductor elements among the semiconductor elements. The discharge inhibitor is bonded not to a surface of a center of each semiconductor element among the semiconductor elements but to a surface of the inter-element portion. The discharge inhibitor is made of an insulator.
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