公开(公告)号：US06661971B2

公开(公告)日：2003-12-09

申请号：US10106987

申请日：2002-03-26

申请人： Mitsuo Manabe ,  Kenji Yamane ,  Yukihiro Kaneko

发明人： Mitsuo Manabe ,  Kenji Yamane ,  Yukihiro Kaneko

IPC分类号： G03B300

CPC分类号： G03B13/18

摘要： Provided is a camera capable of contributing reductions in the number of components and manufacturing costs. A holding member is mounted on a top portion of a camera body. A block portion for holding a device for range-finding, a finder and so on, a semicylindrical portion for holding a battery, and a plate portion for holding a gear train of the camera body are integrally combined to form the holding member. Therefore, the number of components of the camera can be reduced, thereby resulting in a reduction in the manufacturing costs.

摘要翻译： 提供了能够减少部件数量和制造成本的相机。 保持构件安装在照相机主体的顶部。 用于保持测距装置，取景器等的块部分，用于保持电池的半圆柱形部分和用于保持照相机主体的齿轮系的板部分被一体地组合以形成保持构件。 因此，可以减少相机的部件数量，从而导致制造成本的降低。

公开(公告)号：US06567616B2

公开(公告)日：2003-05-20

申请号：US10109321

申请日：2002-03-27

申请人： Yukihiro Kaneko ,  Mitsuo Manabe

发明人： Yukihiro Kaneko ,  Mitsuo Manabe

IPC分类号： G03B1336

CPC分类号： G03B13/00

摘要： In a camera provided with an instrument supporting frame, with which a light projecting device or a light receiving device of an automatic focusing apparatus are combined at a predetermined position, a retaining piece, which is capable of elastically pushing and holding the light projecting device or the light receiving device at the predetermined position, is formed through integral molding together with the instrument supporting frame. The device is held by the retaining piece at the predetermined position and is adhered in this state to the instrument supporting frame by use of an adhesive agent.

公开(公告)号：US08427202B2

公开(公告)日：2013-04-23

申请号：US13305459

申请日：2011-11-28

申请人： Yukihiro Kaneko

发明人： Yukihiro Kaneko

IPC分类号： H03K19/173 ,  G11C11/22

CPC分类号： H03K19/17796 ,  H03K19/17748

摘要： A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes.

摘要翻译： 非易失性逻辑电路包括逻辑配置电极和输入电极。 非逻辑逻辑电路可编程为从逻辑连接（AND），逻辑分离（OR），逻辑非连接（NAND），逻辑非分离（NOR）和逻辑独占分离（NOR）之间选择的输入信号之间的任何逻辑电路 （XOR），通过将施加的电压改变为逻辑配置电极。

公开(公告)号：US20110299566A1

公开(公告)日：2011-12-08

申请号：US13207940

申请日：2011-08-11

申请人： Michihito Ueda ,  Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Eiji Fujii

发明人： Michihito Ueda ,  Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Eiji Fujii

IPC分类号： G01K7/36

CPC分类号： H01L37/02 ,  G01K7/36

摘要： A temperature sensor includes first and second lower electrodes, a ferroelectric layer having polarization, a semiconductor layer; and first to third upper electrodes. The second upper electrode is interposed between the first upper electrode and the third upper electrode in a plan view. The semiconductor layer includes a first channel disposed between the first upper electrode and the second upper electrode, and a second channel disposed between the second upper electrode and the third upper electrode. The ferroelectric layer includes a first ferroelectric part disposed below the first channel and a second ferroelectric part disposed below the second channel. A polarization direction of the first ferroelectric part is opposite to a polarization direction of the second first ferroelectric part. The temperature is calculated based on the output voltage from the second upper electrode and the voltage applied to the first upper electrode.

摘要翻译： 温度传感器包括第一和第二下部电极，具有极化的铁电体层，半导体层; 和第一至第三上电极。 第二上电极在平面图中插入在第一上电极和第三上电极之间。 半导体层包括设置在第一上电极和第二上电极之间的第一通道和设置在第二上电极和第三上电极之间的第二通道。 铁电层包括设置在第一通道下方的第一铁电体部分和设置在第二通道下方的第二铁电体部分。 第一铁电体部的偏振方向与第二第一强电介质部的偏振方向相反。 基于来自第二上电极的输出电压和施加到第一上电极的电压来计算温度。

公开(公告)号：US20080251816A1

公开(公告)日：2008-10-16

申请号：US12033481

申请日：2008-02-19

申请人： Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Yoshihisa Kato

发明人： Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Yoshihisa Kato

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28291 ,  H01L27/11502 ,  H01L29/6684 ,  H01L29/78391

摘要： A semiconductor memory device is composed of a field effect transistor using the interface between a ferroelectric film and a semiconductor film as the channel and including a gate electrode to which a voltage for controlling the polarization state of the ferroelectric film is applied and source/drain electrodes provided on both ends of the channel to detect a current flowing in the channel in accordance with the polarization state. The semiconductor film is made of a material having a spontaneous polarization and the direction of the spontaneous polarization is parallel with the interface between the ferroelectric film and the semiconductor film.

摘要翻译： 半导体存储器件由使用铁电体膜和半导体膜之间的界面作为沟道的场效应晶体管构成，并且包括施加用于控制强电介质膜的极化状态的电压的栅电极和源极/漏极 设置在通道的两端，以根据偏振状态检测在通道中流动的电流。 半导体膜由具有自发极化的材料制成，并且自发极化的方向与铁电体膜和半导体膜之间的界面平行。

公开(公告)号：US20070148585A1

公开(公告)日：2007-06-28

申请号：US11473348

申请日：2006-06-22

申请人： Yukihiro Kaneko ,  Kaoru Suzuki ,  Minoru Tamura ,  Yoshiyasu Kubo

发明人： Yukihiro Kaneko ,  Kaoru Suzuki ,  Minoru Tamura ,  Yoshiyasu Kubo

IPC分类号： G03C1/00

CPC分类号： C08F212/14 ,  G03F7/0392 ,  G03F7/0395

摘要： The present invention provides a hyperbranched polymer suitable as a polymer material for nanofabrication, in particular, photolithography. The hyperbranched polymer of the present invention is characterized by having a core portion prepared by a living radical polymerization of chloromethyl styrene or the like, and an acid decomposition group such as p-tert-butoxy styrene, which is linked to the core portion and present at the end of a molecule of the polymer.

摘要翻译： 本发明提供了一种适用于纳米加工的高分子材料的超支化聚合物，特别是光刻法。 本发明的超支化聚合物的特征在于具有通过氯甲基苯乙烯等的活性自由基聚合制备的核心部分和与核心部分连接并存在的酸分解基团如对叔丁氧基苯乙烯 在聚合物分子的末端。

公开(公告)号：US4623992A

公开(公告)日：1986-11-18

申请号：US558742

申请日：1983-12-06

申请人： Masanori Kurosaki ,  Yoshio Aoyagi ,  Yoshiharu Ueki ,  Yukihiro Kaneko ,  Minoru Motohashi ,  Shozaburo Sakaguchi ,  Manabu Sawaki

发明人： Masanori Kurosaki ,  Yoshio Aoyagi ,  Yoshiharu Ueki ,  Yukihiro Kaneko ,  Minoru Motohashi ,  Shozaburo Sakaguchi ,  Manabu Sawaki

IPC分类号： G11B15/675 ,  G11B31/00 ,  G11B33/00 ,  G11B33/10 ,  H05K5/00 ,  H04B1/20 ,  H04B1/08

CPC分类号： H05K5/0017 ,  G11B15/675 ,  G11B31/003 ,  G11B33/00 ,  G11B33/10

摘要： In a cassette tape deck having a cover panel for covering an opening into which a tape cassette may be inserted, a keyboard section with dials for operating the tape deck and a display section with display elements for displaying operating conditions of the tape deck are provided on both front and rear surfaces of the cover panel of the tape deck.

摘要翻译： 在具有用于覆盖可插入带盒的开口的盖板的盒式磁带机架中，具有用于操作磁带机的拨盘的键盘部分和具有用于显示磁带机的操作条件的显示元件的显示部分设置在 胶带甲板的盖板的前表面和后表面。

公开(公告)号：US20120217996A1

公开(公告)日：2012-08-30

申请号：US13465880

申请日：2012-05-07

申请人： Yukihiro Kaneko

发明人： Yukihiro Kaneko

IPC分类号： H03K19/173

CPC分类号： H03K19/17796 ,  H03K19/17748

摘要： A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes.

公开(公告)号：US08228708B2

公开(公告)日：2012-07-24

申请号：US13222658

申请日：2011-08-31

申请人： Yukihiro Kaneko ,  Hiroyuki Tanaka ,  Michihito Ueda

发明人： Yukihiro Kaneko ,  Hiroyuki Tanaka ,  Michihito Ueda

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  H01L27/1159 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/78648

摘要： In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2

摘要翻译： 在半导体存储器件的操作方法中，（1）对第一栅电极施加满足V1> Vs，V1> Vd，V2> Vs，V2> Vd的电压V1，V2，Vs，Vd， 分别写入第一电阻值的第二栅电极，源电极和漏电极，（2）满足V1> Vs，V1> Vd，V2

公开(公告)号：US07732847B2

公开(公告)日：2010-06-08

申请号：US12033481

申请日：2008-02-19

申请人： Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Yoshihisa Kato

发明人： Hiroyuki Tanaka ,  Yukihiro Kaneko ,  Yoshihisa Kato

IPC分类号： H01L31/113

CPC分类号： H01L21/28291 ,  H01L27/11502 ,  H01L29/6684 ,  H01L29/78391

摘要： A semiconductor memory device is composed of a field effect transistor using the interface between a ferroelectric film and a semiconductor film as the channel and including a gate electrode to which a voltage for controlling the polarization state of the ferroelectric film is applied and source/drain electrodes provided on both ends of the channel to detect a current flowing in the channel in accordance with the polarization state. The semiconductor film is made of a material having a spontaneous polarization and the direction of the spontaneous polarization is parallel with the interface between the ferroelectric film and the semiconductor film.

摘要翻译： 半导体存储器件由使用铁电体膜和半导体膜之间的界面作为沟道的场效应晶体管构成，并且包括施加用于控制强电介质膜的极化状态的电压的栅电极和源极/漏极 设置在通道的两端，以根据偏振状态检测在通道中流动的电流。 半导体膜由具有自发极化的材料制成，并且自发极化的方向与铁电体膜和半导体膜之间的界面平行。