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    Gigabit switch on chip architecture
    6.
    发明授权
    Gigabit switch on chip architecture 有权
    千兆开关芯片架构

    公开(公告)号：US07675924B2

    公开(公告)日：2010-03-09

    申请号：US11490109

    申请日：2006-07-21

    申请人： Govind Malalur ,  Shiri Kadambi ,  Shekhar Ambe ,  Mohan Kalkunte

    发明人： Govind Malalur ,  Shiri Kadambi ,  Shekhar Ambe ,  Mohan Kalkunte

    IPC分类号： H04L12/56 ,  H04L12/28

    CPC分类号： G06F13/4022

    摘要： A data switch for network communications includes a first data port interface and a second data port interface is provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and a common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.

    摘要翻译： 用于网络通信的数据交换机包括第一数据端口接口，并且提供支持至少一个数据端口发送和接收数据的第二数据端口接口。 提供了CPU接口，CPU接口配置为与CPU进行通信。 提供通用存储器，并与第一数据端口接口和第二数据端口接口通信。 提供存储器管理单元，并且传送来自第一数据端口接口和第二数据端口接口的数据以及公共存储器。 提供至少两组通信信道，其中每个通信信道在第一数据端口接口，第二数据端口接口和存储器管理单元之间传送数据和消息传递信息。

    Cluster switching architecture
    7.
    发明授权
    Cluster switching architecture 有权
    集群交换架构

    公开(公告)号：US07295552B1

    公开(公告)日：2007-11-13

    申请号：US09642917

    申请日：2000-08-19

    申请人： Shiri Kadambi ,  Mohan Kalkunte ,  Shekhar Ambe

    发明人： Shiri Kadambi ,  Mohan Kalkunte ,  Shekhar Ambe

    IPC分类号： H04L12/28

    CPC分类号： H04L12/4645 ,  H04L12/467 ,  H04L12/66 ,  H04L49/109 ,  H04L49/3036 ,  H04L49/3072 ,  H04L49/351 ,  H04L49/352 ,  H04L49/45

    摘要： A network switch including at least one data port interface supporting a plurality of data ports, at least one stack link interface configured to transmit data between the network switch and other network switches, and a CPU interface configured to communicate with a CPU. A memory management unit in communication with the at least one data port interface and the at least one stack link interface is provided along with a memory interface in communication with the at least one data port interface and the at least one stack link interface, wherein the memory interface is configured to communicate with a memory. A communication channel is provided for communicating data and messaging information between the at least one data port interface, the at least one stack link interface, the memory interface, and the memory management unit, wherein the memory management unit is configured to route data received from each of the at least one data port interface and the at least one stack link interface to the memory interface.

    摘要翻译： 一种网络交换机，包括支持多个数据端口的至少一个数据端口接口，配置成在网络交换机和其他网络交换机之间传输数据的至少一个堆叠链路接口，以及被配置为与CPU通信的CPU接口。 与所述至少一个数据端口接口和所述至少一个堆叠链路接口通信的存储器管理单元与与所述至少一个数据端口接口和所述至少一个堆叠链路接口通信的存储器接口一起提供，其中， 存储器接口被配置为与存储器通信。 提供通信信道，用于在所述至少一个数据端口接口，所述至少一个堆叠链路接口，所述存储器接口和所述存储器管理单元之间传送数据和消息传递信息，其中所述存储器管理单元被配置为路由从 所述至少一个数据端口接口和所述至少一个堆叠链路中的每一个到所述存储器接口。

    Gigabit switch on chip architecture
    8.
    发明申请
    Gigabit switch on chip architecture 有权

    公开(公告)号：US20060274786A1

    公开(公告)日：2006-12-07

    申请号：US11490109

    申请日：2006-07-21

    申请人： Govind Malalur ,  Shiri Kadambi ,  Shekhar Ambe ,  Mohan Kalkunte

    发明人： Govind Malalur ,  Shiri Kadambi ,  Shekhar Ambe ,  Mohan Kalkunte

    IPC分类号： H04J3/22

    CPC分类号： G06F13/4022

    摘要： A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One set of communication channels provides communication from the first and second data port interfaces to the memory management unit and the other set of communication channels provides communication from the memory management unit to the first and second data port interfaces.

    Method for avoiding out-of-ordering of frames in a network switch
    9.
    发明授权
    Method for avoiding out-of-ordering of frames in a network switch 失效
    避免网络交换机中帧失序的方法

    公开(公告)号：US07145869B1

    公开(公告)日：2006-12-05

    申请号：US09527856

    申请日：2000-03-17

    申请人： Shiri Kadambi ,  Mohan Kalkunte ,  Shekhar Ambe

    发明人： Shiri Kadambi ,  Mohan Kalkunte ,  Shekhar Ambe

    IPC分类号： H04L12/28 ,  H04L12/56

    CPC分类号： H04L47/20 ,  H04L47/10 ,  H04L47/125 ,  H04L47/30 ,  H04L49/201 ,  H04L49/351 ,  H04L49/552

    摘要： A method for avoiding out-of-ordering of frames in a network, wherein the method includes the steps of providing at least one first type of queue in a network switch, providing at least one second type of queue in a network switch, and receiving an incoming packet. The method further includes first storing the incoming packet in the at least one first type of queue if the packet is from a first source, second storing the incoming packet in the at least one second type of queue if the packet is from a second source, and sending the incoming packet to a desired destination. Additionally, a method for avoiding out-of-ordering of frames in a network including the steps of receiving an incoming packet at a network switch, determining if the incoming packet is from a high speed source, first storing the incoming packet in a first type of queue, if the incoming packet is from said high speed source, and second storing the incoming packet in a second type of queue, if the incoming packet is from a lower speed source. Additionally, a step of sending the incoming packet stored in one of the first queue and the second queue using a first-in first-out operation.

    摘要翻译： 一种用于避免网络中帧的排序不足的方法，其中所述方法包括以下步骤：在网络交换机中提供至少一种第一类型的队列，在网络交换机中提供至少一种第二类型的队列，以及接收 传入数据包。 所述方法还包括：如果所述分组来自第一源，则首先将所述输入分组存储在所述至少一个第一类型的队列中;如果所述分组来自第二来源，则将所述输入分组存储在所述至少一种第二类型的队列中; 并将输入的分组发送到期望的目的地。 另外，一种用于避免网络中的帧排序不足的方法，包括以下步骤：在网络交换机处接收输入分组，确定输入分组是否来自高速源，首先将输入分组存储为第一类型 如果进入的分组来自所述高速源，并且如果进入的分组来自较低速度的源，则将所述入局分组存储在第二类型的队列中。 另外，使用先进先出操作来发送存储在第一队列和第二队列之一中的传入分组的步骤。

    Method and apparatus for filtering packets based on flows using address tables
    10.
    发明授权
    Method and apparatus for filtering packets based on flows using address tables 失效

    公开(公告)号：US07099336B2

    公开(公告)日：2006-08-29

    申请号：US09931754

    申请日：2001-08-20

    申请人： Mohan Kalkunte ,  Shekhar Ambe ,  Shiri Kadambi

    发明人： Mohan Kalkunte ,  Shekhar Ambe ,  Shiri Kadambi

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30 ,  H04L49/3018 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354

    摘要： A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One data port interface of the first and second data port interfaces has a fast filtering processor for filtering the data coming into the one data port interface, and taking selective filter action based upon a filtering result. Also the one data port interface includes a flow monitor for monitoring flows of data through the network switch, where a flow of data is defined by a combination of a source address and a destination address for a portion of the data passing through the network switch.