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1.发明申请METHOD AND APPARATUS FOR JITTER COMPENSATION IN RECEIVER CIRCUITS USING NONLINEAR DYNAMIC PHASE SHIFTING TECHNIQUE BASED ON BIT HISTORY PATTERN 有权使用基于BIT历史图案的非线性动态相位移动技术的接收器电路中抖动补偿的方法和装置公开(公告)号：US20090168931A1
公开(公告)日：2009-07-02
申请号：US11966269
申请日：2007-12-28
CPC分类号： H04L7/0338 , H04L1/205 , H04L7/0083
摘要： The present invention provides a simple, easy to implement method and apparatus to reduce jitter in a channel and expand the eye width and eye height of the eye pattern of the signal. The method and apparatus of the present invention reduces jitter specific to a channel in a high speed interface. The present invention utilizes a phasing shifting mechanism based on history of the incoming bits at the receiver. The input bits from the channel are shifted in time before getting to the receiver. This approach significantly reduces Intersymbol Interference (ISI) and deterministic jitter, thus opening up the eye width and eye height for a given interface.
摘要翻译： 本发明提供了一种简化，易于实现的方法和装置，用于减少信道中的抖动并扩大信号眼图的眼睛宽度和眼睛高度。 本发明的方法和装置减少了在高速接口中专用于信道的抖动。 本发明基于接收机的输入位的历史来利用相位移位机构。 来自通道的输入位在到达接收机之前被及时移位。 这种方法显着地减少了符号间干扰（ISI）和确定性抖动，从而打开给定接口的眼睛宽度和眼睛高度。
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2.发明授权Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern 有权使用基于位历史模式的非线性动态相移技术在接收机电路中进行抖动补偿的方法和装置公开(公告)号：US07944963B2
公开(公告)日：2011-05-17
申请号：US11966269
申请日：2007-12-28
IPC分类号： H04B17/00
CPC分类号： H04L7/0338 , H04L1/205 , H04L7/0083
摘要： The present invention provides a simple, easy to implement method and apparatus to reduce jitter in a channel and expand the eye width and eye height of the eye pattern of the signal. The method and apparatus of the present invention reduces jitter specific to a channel in a high speed interface. The present invention utilizes a phasing shifting mechanism based on history of the incoming bits at the receiver. The input bits from the channel are shifted in time before getting to the receiver. This approach significantly reduces Intersymbol Interference (ISI) and deterministic jitter, thus opening up the eye width and eye height for a given interface.
摘要翻译： 本发明提供了一种简化，易于实现的方法和装置，用于减少信道中的抖动并扩大信号眼图的眼睛宽度和眼睛高度。 本发明的方法和装置减少了在高速接口中专用于信道的抖动。 本发明基于接收机的输入位的历史来利用相位移位机构。 来自通道的输入位在到达接收机之前被及时移位。 这种方法显着地减少了符号间干扰（ISI）和确定性抖动，从而打开给定接口的眼睛宽度和眼睛高度。
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公开(公告)号：US08402406B2
公开(公告)日：2013-03-19
申请号：US12979745
申请日：2010-12-28
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
CPC分类号： G06F17/5068 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.
摘要翻译： 公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。 在一个实施例中，谐振优化器确定将芯片连接到半导体芯片基座的衬底的接合线的性能特性。 在该实施例中，谐振优化器基于接合线的性能特性，选择从衬底的信号互连延伸到衬底的周边的开放式电镀短截线的线宽度。谐振优化器还产生 用于衬底的信号迹线的设计，其中信号迹线包括具有所选线宽的开口电镀短截线。
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公开(公告)号：US08319113B2
公开(公告)日：2012-11-27
申请号：US12797244
申请日：2010-06-09
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4697 , Y10T29/49124 , Y10T29/49155
摘要： A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.
摘要翻译： 一种具有降低的介质损耗的印刷电路板（PCB），包括设置在介电材料层上的导电迹线，所述介电材料层包括芯层和预浸料层，介电材料层中的一个或多个包括空气袋， PCB的总相对介电常数。
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公开(公告)号：US20120167033A1
公开(公告)日：2012-06-28
申请号：US12979745
申请日：2010-12-28
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.
摘要翻译： 公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。 实施例包括通过谐振优化器确定接合线的性能特征，将芯片连接到半导体芯片基座的衬底的接合线; 基于所述接合线的性能特性，通过所述共振优化器选择所述开口电镀短截线的线宽，所述开口电镀短截线从所述基板的信号互连延伸到所述基板的周围; 并且通过所述谐振优化器产生用于所述衬底的信号迹线的设计，所述信号迹线包括具有所选线宽度的开放式电镀短截线。
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公开(公告)号：US08269505B2
公开(公告)日：2012-09-18
申请号：US12638044
申请日：2009-12-15
IPC分类号： G01R31/28
CPC分类号： G01R31/2812
摘要： One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
摘要翻译： 一个实施例提供了一种定位印刷电路板中的短路的方法。 测试信号可以在电路板上的不同测试点注入。 每个测试点和短路之间的距离可以根据短路信号反射传播回每个测试点所需的时间来确定。 各种测试点和短路之间的距离可用于缩小短路的可能位置，甚至可以精确定位短路位置。
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公开(公告)号：US20110303445A1
公开(公告)日：2011-12-15
申请号：US12797244
申请日：2010-06-09
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4697 , Y10T29/49124 , Y10T29/49155
摘要： A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.
摘要翻译： 一种具有降低的介电损耗的印刷电路板（“PCB”），包括设置在电介质材料层上的导电迹线，介电材料层包括芯层和预浸料层，介电材料层中的一层或多层包括空气袋 降低PCB的整体相对介电常数。
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公开(公告)号：US09338881B2
公开(公告)日：2016-05-10
申请号：US13531959
申请日：2012-06-25
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4697 , Y10T29/49124 , Y10T29/49155
摘要： In a particular embodiment, a method of manufacturing a printed circuit board (‘PCB’) with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.
摘要翻译： 在特定实施例中，制造具有降低的介电损耗的印刷电路板（“PCB”）的方法包括制造设置在电介质材料层上的导电迹线; 以及制造包括芯层和预浸料层的介电材料层，其中一个或多个介电材料层包括空气袋，其减小PCB的总体相对介电常数。 在特定实施例中，导电迹线相对于彼此正交地布置在电介质材料的层上，并且空气袋相对于导电迹线以45度的角度对准。
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公开(公告)号：US20110140709A1
公开(公告)日：2011-06-16
申请号：US12638044
申请日：2009-12-15
CPC分类号： G01R31/2812
摘要： One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
摘要翻译： 一个实施例提供了一种定位印刷电路板中的短路的方法。 测试信号可以在电路板上的不同测试点注入。 每个测试点和短路之间的距离可以根据短路信号反射传播回每个测试点所需的时间来确定。 各种测试点和短路之间的距离可用于缩小短路的可能位置，甚至可以精确定位短路位置。
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公开(公告)号：US08901946B2
公开(公告)日：2014-12-02
申请号：US12785572
申请日：2010-05-24
CPC分类号： G01R31/2813 , G01R31/2815
摘要： Apparatus and methods for identifying a signal on a printed circuit board (‘PCB’) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.
摘要翻译： 用于识别被测PCB板上的信号的装置和方法，包括安装在PCB上的集成电路，该集成电路具有测试信号发生器，该测试信号发生器将测试信号发送到集成电路的输出引脚 ，输出引脚连接到PCB上的测试点; 该集成电路还具有插入到测试信号中的信号识别逻辑，该信号的标识符; 与测试点接触的测试探针; 以及信号识别控制器，其从测试探针接收测试信号和标识符，并根据标识符显示信号的身份。
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