公开(公告)号：US07247915B2

公开(公告)日：2007-07-24

申请号：US11375778

申请日：2006-03-15

Applicant: Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L21/28518 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833

Abstract: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

Abstract translation: 一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。 然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

公开(公告)号：US20070152306A1

公开(公告)日：2007-07-05

申请号：US11324334

申请日：2006-01-04

Applicant: Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

Inventor： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

IPC: H01L23/58 ,  H01L21/4763

CPC classification number: H01L21/2885 ,  C23C18/1889 ,  C23C18/1893 ,  C25D5/54 ,  C25D13/04 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877

Abstract: A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the metal layer are formed sequentially on the conductive substrate or the conductive layer, wherein the electroactive organic layer comprises metal atoms and serves as a seed layer, resulting in the metal layer formed in-situ.

Abstract translation: 半导体器件及其制造方法。 半导体器件包括基底，具有适形阶梯覆盖和均匀厚度的电活性有机层和金属层。 衬底是其上形成有导电层的导电衬底或非导电衬底。 所述电活性有机层和所述金属层依次形成在所述导电性基板或所述导电层上，其中所述电活性有机层包含金属原子并且用作种子层，导致所述金属层原位形成。

公开(公告)号：US20060157800A1

公开(公告)日：2006-07-20

申请号：US11375778

申请日：2006-03-15

Applicant: Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L29/40

CPC classification number: H01L21/28518 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833

Abstract: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

Abstract translation: 一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。 然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

公开(公告)号：US20050277298A1

公开(公告)日：2005-12-15

申请号：US11201845

申请日：2005-08-11

Applicant: Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L33/00

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract translation: 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

公开(公告)号：US20060246727A1

公开(公告)日：2006-11-02

申请号：US11115693

申请日：2005-04-27

Applicant: Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

Inventor： Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

IPC: H01L21/311 ,  H01L21/306 ,  C23C16/00

CPC classification number: H01L21/76873 ,  H01L21/02063 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76843

Abstract: An integrated apparatus comprises a plasma etching station, a wet cleaning station, a de-gassing station, a thin film deposition station, and a wafer transfer mechanism to automatically index wafers between the stations in a predetermined processing order.

Abstract translation: 集成装置包括等离子体蚀刻站，湿式清洁站，除气站，薄膜沉积站和晶片传送机构，用于以预定的处理顺序自动地在台站之间索引晶片。

公开(公告)号：US20050029665A1

公开(公告)日：2005-02-10

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US20050006776A1

公开(公告)日：2005-01-13

申请号：US10618536

申请日：2003-07-11

Applicant: Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L33/00

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

公开(公告)号：US06806192B2

公开(公告)日：2004-10-19

申请号：US10350837

申请日：2003-01-24

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US07443029B2

公开(公告)日：2008-10-28

申请号：US11201845

申请日：2005-08-11

Applicant: Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract translation: 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

公开(公告)号：US06245675B1

公开(公告)日：2001-06-12

申请号：US09489966

申请日：2000-01-24

Applicant: Mong-Song Liang ,  Shau-Lin Shue

Inventor： Mong-Song Liang ,  Shau-Lin Shue

IPC: H01L214763

CPC classification number: H01L21/76879

Abstract: A new method of metallization using a three-dimensional aluminum reservoir to increase the electromigration lifetime of a tungsten plug in the fabrication of integrated circuits is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. Aluminum lines are formed over the insulating layer. An intermetal dielectric layer is deposited overlying the aluminum lines. Via openings are made through the intermetal dielectric layer to the aluminum lines. Aluminum is selectively deposited into the via openings to form aluminum reservoirs in the bottom of the via openings wherein the aluminum does not completely fill the via openings. Tungsten plugs are formed within the via openings overlying the aluminum reservoirs wherein the aluminum reservoirs provide a source for electrons to replenish electrons lost through electromigration to complete formation of tungsten plug metallization with increased electromigration lifetime in the fabrication of integrated circuits.

Abstract translation: 实现了在集成电路制造中使用三维铝储存器来增加钨插塞的电迁移寿命的新的金属化方法。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 在绝缘层上形成铝线。 金属间电介质层沉积在铝线上。 通过开口穿过金属间电介质层到铝线。 选择性地将铝沉积到通孔开口中以在通孔开口的底部形成铝储存器，其中铝不完全填充通孔。 钨插塞形成在覆盖铝储存器的通孔开口中，其中铝储存器提供电子源以补充通过电迁移损失的电子，以在集成电路的制造中增加电迁移寿命来完成钨插塞金属化的形成。