公开(公告)号：US20060246727A1

公开(公告)日：2006-11-02

申请号：US11115693

申请日：2005-04-27

申请人： Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

发明人： Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

IPC分类号： H01L21/311 ,  H01L21/306 ,  C23C16/00

CPC分类号： H01L21/76873 ,  H01L21/02063 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76843

摘要： An integrated apparatus comprises a plasma etching station, a wet cleaning station, a de-gassing station, a thin film deposition station, and a wafer transfer mechanism to automatically index wafers between the stations in a predetermined processing order.

摘要翻译： 集成装置包括等离子体蚀刻站，湿式清洁站，除气站，薄膜沉积站和晶片传送机构，用于以预定的处理顺序自动地在台站之间索引晶片。

公开(公告)号：US6015735A

公开(公告)日：2000-01-18

申请号：US6509

申请日：1998-01-13

申请人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

发明人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/302

CPC分类号： H01L27/1085 ,  H01L28/86

摘要： The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

摘要翻译： 本发明公开了一种用于形成DRAM电容器的方法，该DRAM电容器通过利用首先沉积掺杂和未掺杂电介质材料的交替层的沉积工艺具有改善的电荷存储容量，然后将深UV型光致抗蚀剂层沉积在氧化物层的顶部 使得在用于电池开口的高密度等离子体蚀刻工艺期间，当在蚀刻室中暴露于UV发射时，光致抗蚀剂层产生酸性反应产物，使得电池开口的侧壁以不均匀的方式横向蚀刻，即， 掺杂的介电层比非掺杂的介电层更严格地被蚀刻，从而形成额外的表面积和改善的形成的电容器的电荷存储容量。

公开(公告)号：US06319822B1

公开(公告)日：2001-11-20

申请号：US09164999

申请日：1998-10-01

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

公开(公告)号：US20080093682A1

公开(公告)日：2008-04-24

申请号：US11583491

申请日：2006-10-18

申请人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L29/76

CPC分类号： H01L21/823443 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

摘要： Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.

摘要翻译： 提供了具有硅化物栅电极和制造方法的半导体结构。 一种器件包括形成在第一有源区中的第一硅化结构和形成在第二有源区中的第二硅化结构。 两个硅化物结构具有不同的金属浓度。 形成硅化器件的方法包括在第一和第二器件制造区域上形成多晶硅结构。 实施例包括用金属替代第一器件制造区上的多晶硅结构的第一部分，并用金属代替第二器件制造区上的多晶硅结构的第二部分。 优选地，第二部分不同于第一部分。 实施例还包括使第一和第二器件制造区上的多晶硅结构与金属反应以形成硅化物。

公开(公告)号：US20070026668A1

公开(公告)日：2007-02-01

申请号：US11457888

申请日：2006-07-17

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/465

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20050095869A1

公开(公告)日：2005-05-05

申请号：US10701825

申请日：2003-11-05

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 通过使用包含氟和氧的高密度，高自由基浓度的等离子体蚀刻底部蚀刻停止层来去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，以最小化底部的铜的反溅射 蚀刻停止层和由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20080242108A1

公开(公告)日：2008-10-02

申请号：US11730551

申请日：2007-04-02

申请人： Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

发明人： Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

IPC分类号： H01L21/46

CPC分类号： H01L21/28079 ,  H01L21/28088 ,  H01L21/67207

摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括提供第一室和第二室。 第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及 在第二室中的金属膜上沉积含硅膜。

公开(公告)号：US08148270B2

公开(公告)日：2012-04-03

申请号：US12727338

申请日：2010-03-19

申请人： Hun-Jan Tao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20100173499A1

公开(公告)日：2010-07-08

申请号：US12727338

申请日：2010-03-19

申请人： Hun-Jan Tao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/306

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20070296002A1

公开(公告)日：2007-12-27

申请号：US11475707

申请日：2006-06-27

申请人： Mong Song Liang ,  Hun-Jan Tao

发明人： Mong Song Liang ,  Hun-Jan Tao

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/7843

摘要： A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a dielectric layer having a first surface and a second surface opposite the first surface wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate, and a contact plug in the dielectric layer, wherein the contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.

摘要翻译： 半导体结构包括具有第一表面和与第一表面相对的第二表面的半导体衬底，在半导体衬底的第一表面上的栅极电介质，栅极电介质上的栅电极，具有至少一部分的源/漏区 在所述半导体衬底中，具有第一表面和与所述第一表面相对的第二表面的电介质层，其中所述电介质层的所述第一表面邻接所述半导体衬底的第二表面，以及所述电介质层中的接触插塞，其中所述接触插塞 从源极/漏极区域的底部延伸到电介质层的第二表面。