公开(公告)号：US06797629B2

公开(公告)日：2004-09-28

申请号：US10185104

申请日：2002-06-27

申请人： Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

发明人： Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

IPC分类号： H01L21302

CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

摘要翻译： 本发明涉及纳米晶体管的制造方法。 本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。 此外，本发明包括在给定下面的硅衬底的区域上形成N阱和P阱，使得可以将给定的电压单独地施加到NMOS晶体管和PMOS晶体管。 因此，本发明可以控制阈值电压以防止漏电流的增加。

公开(公告)号：US5753544A

公开(公告)日：1998-05-19

申请号：US499255

申请日：1995-07-07

申请人： Won Ju Cho ,  Jae Sung Roh

发明人： Won Ju Cho ,  Jae Sung Roh

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L21/2022 ,  H01L29/66765 ,  H01L29/78654 ,  H01L29/78675 ,  H01L29/78678

摘要： A crystallization process comprising the steps of depositing a polycrystalline silicon layer on a semiconductor substrate, implanting silicon ions into first and second areas of the polycrystalline silicon layer in different amounts such that crystals having a predetermined plane direction remain in the second area and such that the first area becomes amorphous, and performing a thermal treatment to recrystallize the amorphous second area using the crystals having the predetermined plane direction remaining in the first area as a nucleus.

摘要翻译： 一种结晶方法，包括以下步骤：在半导体衬底上沉积多晶硅层，以不同的量将硅离子注入多晶硅层的第一和第二区域，使得具有预定平面方向的晶体保留在第二区域中， 第一区域变为无定形，并且使用具有保留在第一区域中的预定平面方向的晶体作为核，进行热处理以使无定形第二区域再结晶。

公开(公告)号：US6117724A

公开(公告)日：2000-09-12

申请号：US410752

申请日：1999-10-01

申请人： Won Ju Cho

发明人： Won Ju Cho

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10808

摘要： A method of fabricating a DRAM cell and the DRAM cell include a substrate, and a bit line formed in a first direction on the substrate. A channel region is then formed on a portion of the bit line. The channel region has a lateral surface extending vertically from the bit line. A first insulating layer is formed over the substrate, excluding the channel region, and is formed on at least a portion of the lateral surface of the channel region. A gate electrode is formed on a portion of the first insulating layer, which is on the portion of the lateral surface of the channel region, and a word line, connected to the gate electrode, is formed in a second direction on the first insulating layer. A second insulating layer is then formed over a portion of the substrate. The second insulating layer has a contact hole which exposes the channel region. Next, a capacitor is formed on a portion of the second insulating layer and on the channel region via the contact hole.

摘要翻译： 制造DRAM单元和DRAM单元的方法包括基板和在基板上沿第一方向形成的位线。 然后在位线的一部分上形成沟道区。 通道区域具有从位线垂直延伸的侧表面。 第一绝缘层形成在衬底上，不包括沟道区，并且形成在沟道区的侧表面的至少一部分上。 栅极电极形成在第一绝缘层的位于沟道区域的侧表面的部分上的部分上，并且连接到栅电极的字线在第一绝缘层上沿第二方向形成 。 然后在基板的一部分上形成第二绝缘层。 第二绝缘层具有露出沟道区的接触孔。 接下来，通过接触孔在第二绝缘层的一部分和沟道区上形成电容器。

公开(公告)号：US6143669A

公开(公告)日：2000-11-07

申请号：US192498

申请日：1998-11-17

申请人： Won Ju Cho

发明人： Won Ju Cho

IPC分类号： H01L29/78 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/31

CPC分类号： H01L21/823462

摘要： A method for manufacturing a gate oxide film in a semiconductor device includes: preparing a semiconductor substrate having a first and a second active region; implanting germanium ions into the first active region; and forming a first and a second gate oxide films on the first and the second active regions, respectively, wherein the first gate oxide film is thicker than the second gate oxide film.

摘要翻译： 一种在半导体器件中制造栅极氧化膜的方法，包括：制备具有第一和第二有源区的半导体衬底; 将锗离子注入第一活性区; 以及分别在所述第一和第二有源区上形成第一和第二栅极氧化膜，其中所述第一栅极氧化物膜比所述第二栅极氧化物膜厚。

公开(公告)号：US5994729A

公开(公告)日：1999-11-30

申请号：US883171

申请日：1997-06-26

申请人： Won Ju Cho

发明人： Won Ju Cho

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10823 ,  H01L27/10808

摘要： A method of fabricating a DRAM cell and the DRAM cell include a substrate, and a bit line formed in a first direction on the substrate. A channel region is then formed on a portion of the bit line. The channel region has a lateral surface extending vertically from the bit line. A first insulating layer is formed over the substrate, excluding the channel region, and is formed on at least a portion of the lateral surface of the channel region. A gate electrode is formed on a portion of the first insulating layer, which is on the portion of the lateral surface of the channel region, and a word line, connected to the gate electrode, is formed in a second direction on the first insulating layer. A second insulating layer is then formed over a portion of the substrate. The second insulating layer has a contact hole which exposes the channel region. Next, a capacitor is formed on a portion of the second insulating layer and on the channel region via the contact hole.