公开(公告)号：US08185687B2

公开(公告)日：2012-05-22

申请号：US13016780

申请日：2011-01-28

申请人： Motohiro Matsuyama ,  Tohru Fukuda ,  Hiroyuki Moro

发明人： Motohiro Matsuyama ,  Tohru Fukuda ,  Hiroyuki Moro

IPC分类号： G06F13/00 ,  G06F9/32

CPC分类号： G06F12/02

摘要： According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

摘要翻译： 根据一个实施例，半导体存储装置包括排队缓冲器，读取模块，分离模块，写入命令发布模块和写入模块。 写命令发布模块被配置为将由写指针信息指示的写地址添加到由分离模块获得的管理数据，以便发出写命令，并将写入命令自动排队到排队缓冲器中。 写入模块被配置为将写命令发布模块发出的写命令提供给非易失性存储器，以便将数据写入到非易失性存储器中。

公开(公告)号：US08359425B2

公开(公告)日：2013-01-22

申请号：US13086240

申请日：2011-04-13

申请人： Kiyotaka Iwasaki ,  Hirotaka Suzuki ,  Tohru Fukuda ,  Motohiro Matsuyama ,  Yoshimasa Aoyama

发明人： Kiyotaka Iwasaki ,  Hirotaka Suzuki ,  Tohru Fukuda ,  Motohiro Matsuyama ,  Yoshimasa Aoyama

IPC分类号： G06F13/00

CPC分类号： G06F3/0632 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679

摘要： According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

摘要翻译： 根据一个实施例，存储器控制装置包括控制器，命令队列模块，多个级处理器和跳过模块。 控制器控制来自主机的非易失性存储器的数据访问命令。 命令队列模块对与数据访问命令对应的传输请求命令进行排队。 舞台处理器各自执行与由命令队列模块排队的传送请求命令相关的舞台处理。 响应于来自控制器的关机命令，跳过模块跳过级处理器的级处理。

公开(公告)号：US20120011303A1

公开(公告)日：2012-01-12

申请号：US13086240

申请日：2011-04-13

申请人： Kiyotaka Iwasaki ,  Hirotaka Suzuki ,  Tohru Fukuda ,  Motohiro Matsuyama ,  Yoshimasa Aoyama

发明人： Kiyotaka Iwasaki ,  Hirotaka Suzuki ,  Tohru Fukuda ,  Motohiro Matsuyama ,  Yoshimasa Aoyama

IPC分类号： G06F12/00

CPC分类号： G06F3/0632 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679

摘要： According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

摘要翻译： 根据一个实施例，存储器控制装置包括控制器，命令队列模块，多个级处理器和跳过模块。 控制器控制来自主机的非易失性存储器的数据访问命令。 命令队列模块对与数据访问命令对应的传输请求命令进行排队。 舞台处理器各自执行与由命令队列模块排队的传送请求命令相关的舞台处理。 响应于来自控制器的关机命令，跳过模块跳过级处理器的级处理。

公开(公告)号：US20120017116A1

公开(公告)日：2012-01-19

申请号：US13082048

申请日：2011-04-07

申请人： Motohiro Matsuyama ,  Hirotaka Suzuki ,  Kiyotaka Iwasaki ,  Tohru Fukuda

发明人： Motohiro Matsuyama ,  Hirotaka Suzuki ,  Kiyotaka Iwasaki ,  Tohru Fukuda

IPC分类号： G06F11/14 ,  G06F11/07

CPC分类号： G06F11/2017 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1068

摘要： According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

摘要翻译： 根据一个实施例，存储器控制装置包括第一控制器，第二控制器，访问模块和响应分类模块。 第一控制器控制从主机向非易失性存储器的数据访问命令的处理。 第二控制器控制分配给第一控制器和第二控制器之间的第二控制器的处理。 响应于来自第一控制器或第二控制器的命令，访问模块执行对非易失性存储器的数据访问。 当访问模块的数据访问发生错误时，响应排序模块返回对第二控制器而不是第一控制器的响应。

公开(公告)号：US09304952B2

公开(公告)日：2016-04-05

申请号：US13205193

申请日：2011-08-08

申请人： Takahiro Nango ,  Hiroyuki Moro ,  Tohru Fukuda

发明人： Takahiro Nango ,  Hiroyuki Moro ,  Tohru Fukuda

IPC分类号： G06F13/16 ,  G11B20/18 ,  G06F3/06

CPC分类号： G06F13/1642 ,  G06F3/0656 ,  G11B20/18

摘要： According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

摘要翻译： 根据一个实施例，存储器控制装置包括：通道中的队列; 第一控制器 发电机; 和第二控制器。 队列保存数据的写入命令。 第一控制器导致：（i）当接收到读命令时，直到写入命令保持在队列中，通道彼此同步，并且写入命令的处理准备好执行，基于读取过程 在写命令之前的read命令; 和（ii）当写入命令的处理准备好执行时，基于写入命令的数据段的通道同步和写入处理。 当通道彼此同步时，发生器基于数据段产生纠错码，并且执行基于写入命令的处理。 第二个控制器将错误校正码写入存储介质。

公开(公告)号：US20120183796A1

公开(公告)日：2012-07-19

申请号：US13498880

申请日：2010-09-27

申请人： Tohru Fukuda ,  Keisuke Sai ,  Remi Kasai

发明人： Tohru Fukuda ,  Keisuke Sai ,  Remi Kasai

IPC分类号： B32B27/08 ,  B05D1/36 ,  B05D3/02

CPC分类号： B05D1/36 ,  B05D7/26 ,  B05D7/50 ,  B05D7/57 ,  B05D7/572 ,  B05D7/5723 ,  B05D2202/10 ,  C08L61/28 ,  C09D133/08 ,  C09D133/10 ,  C09D167/02 ,  Y10T428/31797 ,  C08L2666/16

摘要： There is provided a process for formation of a multi-layered coating film, which includes sequentially coating a first colored coating composition, a second colored coating composition and a clear coating composition (C), and simultaneously heating and curing the obtained first colored coating film, second colored coating film and clear coating film to form a multi-layered coating film, where the first colored coating composition contains (a1) a polyester resin containing a hydroxyl group, which contains 1.0-8.0 mol/kg (resin solid content) of a straight-chain alkylene group having a carbon number of 4 or more in the molecule, has a hydroxyl group value in a range of 30-160 mgKOH/g and has a number-average molecular weight in a range of 1,000-6,000, and (a2) a melamine resin; and the colored coating composition contains (b1) an acrylic resin containing a hydroxyl group, which has a hydroxyl group value in a range of 40-200 mgKOH/g and has a weight-average molecular weight in a range of 3,000-15,000, (b2) a melamine resin having a content rate of a mononuclear melamine of 40 mass % or more, and (b3) an acid catalyst.

摘要翻译： 提供了形成多层涂膜的方法，其包括顺序涂布第一着色涂料组合物，第二着色涂料组合物和透明涂料组合物（C），并同时加热和固化所获得的第一着色涂膜 ，第二着色涂膜和透明涂膜形成多层涂膜，其中第一着色涂料组合物含有（a1）含有羟基的聚酯树脂，其含有1.0-8.0mol / kg（树脂固含量）的 在分子中碳数为4以上的直链亚烷基的羟基值在30〜160mgKOH / g的范围内，数均分子量在1000〜6000的范围内， （a2）三聚氰胺树脂; 着色涂料组合物含有（b1）含有羟基的丙烯酸树脂，其羟基值在40-200mgKOH / g范围内，重均分子量在3,000-15,000范围内（ b2）具有40质量％以上的单核三聚氰胺的含有率的三聚氰胺树脂和（b3）酸催化剂。

公开(公告)号：US08914592B2

公开(公告)日：2014-12-16

申请号：US13299282

申请日：2011-11-17

申请人： Akinori Harasawa ,  Tohru Fukuda

发明人： Akinori Harasawa ,  Tohru Fukuda

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/16 ,  G06F13/16

CPC分类号： G06F3/06 ,  G06F12/16 ,  G06F13/1673

摘要： According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.

摘要翻译： 根据一个实施例，数据存储装置包括写入命令模块，读取命令模块和控制器。 写命令模块被配置为处理用于分别向多个通道的非易失性存储器写入数据的写入命令。 读取命令模块被配置为通常处理读取命令并处理读取修改写入（RMW）操作的读取命令。 控制器被配置为控制读取命令模块，从而在正常读取命令之前执行用于RMW操作的读取命令，从而执行刷新命令，并且控制写入命令模块，从而执行写入冲洗 在执行RMW操作的读取命令之后，包括处理用于RMW操作的写入命令的处理。

公开(公告)号：US08856468B2

公开(公告)日：2014-10-07

申请号：US13278973

申请日：2011-10-21

申请人： Tohru Fukuda

发明人： Tohru Fukuda

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0679 ,  G06F2212/7201

摘要： According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.

摘要翻译： 根据一个实施例，存储器件包括存储器单元，第一存储单元，第二存储单元，第三存储单元，数据移动单元和控制器。 第一存储单元存储逻辑地址和中间地址。 第二存储单元存储对应于中间地址的中间地址和物理地址。 第三存储单元存储对应于逻辑地址和中间地址的标志。 该标志表示通过读取操作读取最新数据是否成功。 当存储在第三存储单元中的标志代表最新数据的读取成功时，控制器确定在数据移动处理期间是否对存储器单元的相同逻辑地址进行写入，并且如果写入已经完成 ，使数据移动处理无效。

公开(公告)号：US20120144094A1

公开(公告)日：2012-06-07

申请号：US13299282

申请日：2011-11-17

申请人： Akinori Harasawa ,  Tohru Fukuda

发明人： Akinori Harasawa ,  Tohru Fukuda

IPC分类号： G06F12/00

CPC分类号： G06F3/06 ,  G06F12/16 ,  G06F13/1673

摘要： According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.

摘要翻译： 根据一个实施例，数据存储装置包括写入命令模块，读取命令模块和控制器。 写命令模块被配置为处理用于分别向多个通道的非易失性存储器写入数据的写入命令。 读取命令模块被配置为通常处理读取命令并处理读取修改写入（RMW）操作的读取命令。 控制器被配置为控制读取命令模块，从而在正常读取命令之前执行用于RMW操作的读取命令，从而执行刷新命令，并且控制写入命令模块，从而执行写入冲洗 在执行RMW操作的读取命令之后，包括处理用于RMW操作的写入命令的处理。

公开(公告)号：US20120140561A1

公开(公告)日：2012-06-07

申请号：US13278973

申请日：2011-10-21

申请人： Tohru Fukuda

发明人： Tohru Fukuda

IPC分类号： G11C16/04

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0679 ,  G06F2212/7201

摘要： According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.

摘要翻译： 根据一个实施例，存储器件包括存储器单元，第一存储单元，第二存储单元，第三存储单元，数据移动单元和控制器。 第一存储单元存储逻辑地址和中间地址。 第二存储单元存储对应于中间地址的中间地址和物理地址。 第三存储单元存储对应于逻辑地址和中间地址的标志。 该标志表示通过读取操作读取最新数据是否成功。 当存储在第三存储单元中的标志代表最新数据的读取成功时，控制器确定在数据移动处理期间是否对存储器单元的相同逻辑地址进行写入，并且如果写入已经完成 ，使数据移动处理无效。