公开(公告)号：US08724357B2

公开(公告)日：2014-05-13

申请号：US13010178

申请日：2011-01-20

申请人： Motoki Imanishi ,  Kenji Sakai ,  Yoshikazu Tanaka

发明人： Motoki Imanishi ,  Kenji Sakai ,  Yoshikazu Tanaka

IPC分类号： H02M7/5387 ,  H02M1/084

CPC分类号： H02M1/08 ,  H03K17/063

摘要： A power semiconductor device comprises: high side and low side switching elements; high side and low side drive circuits; a bootstrap capacitor supplying a drive voltage to the high side drive circuit and having a first terminal connected to a connection point between the high side switching element and the low side switching element and a second terminal connected to a power supply terminal of the high side drive circuit; a bootstrap diode having an anode connected to a power supply and a cathode connected to the second terminal and supplying a current from the power supply to the second terminal; a floating power supply; and a bootstrap compensation circuit supplying a current from the floating power supply to the second terminal, when the high side drive circuit turns ON the high side switching element and the low side drive circuit turns OFF the low side switching element.

摘要翻译： 功率半导体器件包括：高侧和低侧开关元件; 高侧和低侧驱动电路; 向高侧驱动电路供给驱动电压并具有与高侧开关元件和低侧开关元件之间的连接点连接的第一端子的自举电容器和连接到高侧驱动器的电源端子的第二端子 电路 引导二极管，其具有连接到电源的阳极和连接到第二端子的阴极，并且将电流从电源提供给第二端子; 浮动电源; 以及当所述高侧驱动电路导通所述高侧开关元件并且所述低侧驱动电路使所述低侧开关元件断开时，从所述浮动电源向所述第二端子供给电流的自举补偿电路。

公开(公告)号：US08803561B2

公开(公告)日：2014-08-12

申请号：US13228903

申请日：2011-09-09

申请人： Motoki Imanishi ,  Kenji Sakai ,  Yoshikazu Tanaka ,  Kyouko Oyama

发明人： Motoki Imanishi ,  Kenji Sakai ,  Yoshikazu Tanaka ,  Kyouko Oyama

IPC分类号： H03K3/00

CPC分类号： H03K17/162 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.

摘要翻译： 本发明的半导体电路包括：用于响应于ON驱动信号对接通驱动电荷进行充电的电容器;响应于OFF驱动信号而对驱动电荷进行充电的电容器;产生第一触发信号的信号产生电路 响应于ON驱动信号，产生响应于OFF驱动信号产生第二触发信号的信号发生电路，用于响应于第二触发信号对ON驱动电荷进行放电的放电电路，以及用于放电的放电电路 OFF驱动电荷响应于第一触发信号。 利用这种结构，可以提供一种具有通用故障防止功能的半导体电路和半导体器件，通过该功能可以防止由于dV / dt引起的故障，而不受任何外部因素的影响。

公开(公告)号：US20120154007A1

公开(公告)日：2012-06-21

申请号：US13228903

申请日：2011-09-09

申请人： Motoki IMANISHI ,  Kenji Sakai ,  Yoshikazu Tanaka ,  Kyouko Oyama

发明人： Motoki IMANISHI ,  Kenji Sakai ,  Yoshikazu Tanaka ,  Kyouko Oyama

IPC分类号： H03K3/356

CPC分类号： H03K17/162 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.

摘要翻译： 本发明的半导体电路包括：用于响应于ON驱动信号对接通驱动电荷进行充电的电容器;响应于OFF驱动信号而对驱动电荷进行充电的电容器;产生第一触发信号的信号产生电路 响应于ON驱动信号，产生响应于OFF驱动信号产生第二触发信号的信号发生电路，用于响应于第二触发信号对ON驱动电荷进行放电的放电电路，以及用于放电的放电电路 OFF驱动电荷响应于第一触发信号。 利用这种结构，可以提供一种具有通用故障防止功能的半导体电路和半导体器件，通过该功能可以防止由于dV / dt引起的故障，而不受任何外部因素的影响。

公开(公告)号：US20110260707A1

公开(公告)日：2011-10-27

申请号：US13010178

申请日：2011-01-20

申请人： Motoki IMANISHI ,  Kenji Sakai ,  Yoshikazu Tanaka

发明人： Motoki IMANISHI ,  Kenji Sakai ,  Yoshikazu Tanaka

IPC分类号： G05F3/02

CPC分类号： H02M1/08 ,  H03K17/063

摘要： A power semiconductor device comprises: high side and low side switching elements; high side and low side drive circuits; a bootstrap capacitor supplying a drive voltage to the high side drive circuit and having a first terminal connected to a connection point between the high side switching element and the low side switching element and a second terminal connected to a power supply terminal of the high side drive circuit; a bootstrap diode having an anode connected to a power supply and a cathode connected to the second terminal and supplying a current from the power supply to the second terminal; a floating power supply; and a bootstrap compensation circuit supplying a current from the floating power supply to the second terminal, when the high side drive circuit turns ON the high side switching element and the low side drive circuit turns OFF the low side switching element.

摘要翻译： 功率半导体器件包括：高侧和低侧开关元件; 高侧和低侧驱动电路; 向高侧驱动电路供给驱动电压并具有与高侧开关元件和低侧开关元件之间的连接点连接的第一端子的自举电容器和连接到高侧驱动器的电源端子的第二端子 电路 引导二极管，其具有连接到电源的阳极和连接到第二端子的阴极，并且将电流从电源提供给第二端子; 浮动电源; 以及当所述高侧驱动电路导通所述高侧开关元件并且所述低侧驱动电路使所述低侧开关元件断开时，从所述浮动电源向所述第二端子供给电流的自举补偿电路。

公开(公告)号：US08779830B2

公开(公告)日：2014-07-15

申请号：US13802576

申请日：2013-03-13

申请人： Takaki Nakashima ,  Motoki Imanishi ,  Kenji Sakai

发明人： Takaki Nakashima ,  Motoki Imanishi ,  Kenji Sakai

IPC分类号： H03L5/00

CPC分类号： H03K17/063 ,  H03K2217/0063

摘要： A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals.

摘要翻译： 电压转换掩模信号产生电路通过将第一晶体管的输出信号转换为低侧电压来产生第一主信号和第一屏蔽信号，并且通过将第一主信号和第二屏蔽信号的输出信号 第二晶体管为低端电压。 掩模信号生成电路相对于高侧基准电位的波动产生比第一和第二掩模信号高的灵敏度的第三掩模信号。 一种掩模逻辑电路，通过在第一屏蔽信号和第二屏蔽信号之间执行“与”运算，并用第三和第四屏蔽信号屏蔽第一和第二主信号来产生第四屏蔽信号; 以及SR触发器电路，从被掩蔽的第一和第二主信号产生输出信号。

公开(公告)号：US07495482B2

公开(公告)日：2009-02-24

申请号：US11860123

申请日：2007-09-24

申请人： Kenji Sakai ,  Yoshikazu Tanaka

发明人： Kenji Sakai ,  Yoshikazu Tanaka

IPC分类号： H03B1/00

CPC分类号： H02M1/08 ,  H03K17/162 ,  H03K17/284 ,  H03K17/6871 ,  H03K19/018507

摘要： A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals.

摘要翻译： 根据本发明的半导体器件是用于驱动和控制在高电位的主电源电位和主电源电位之间串联连接的两个功率器件的高电位侧的功率器件的半导体器件 低电位，并且配备有脉冲发生电路，用于产生对应于具有第一状态的第一和第二状态的第一和第二状态的电平转变的第一和第二脉冲信号，该第一状态具有示出高电位侧的功率器件的导通和 分别表示高电位侧的功率器件的非导通的第二状态; 电平移位电路，用于通过将第一和第二脉冲信号电平移位到高电位侧来获得第一和第二电平移位脉冲信号; 输入来自设定输入端的第一电平移位脉冲信号和来自复位输入端的第二电平移位脉冲信号的SR型触发电路; 以及用于将SR型触发器电路的输出至少延迟第一和第二脉冲信号的脉冲宽度的延迟电路。

公开(公告)号：US06856166B2

公开(公告)日：2005-02-15

申请号：US10388497

申请日：2003-03-17

申请人： Kenji Sakai ,  Yoshikazu Tanaka

发明人： Kenji Sakai ,  Yoshikazu Tanaka

IPC分类号： H03K5/1532 ,  G06F7/38 ,  H03K5/04 ,  H03K5/135 ,  H03K5/153 ,  H03K19/00 ,  H03K19/173

CPC分类号： H03K5/135 ,  H03K5/04 ,  H03K5/153

摘要： In a status scheme signal processing circuit which obtains a desired output signal on the basis of an OR signal between a pulse output from a one-shot pulse circuit at an edge of an input signal and a status signal, since the input signal and the status signal are not synchronized with each other, the output timing of the output signal changes depending on the timing of the input signal. Therefore, in the present invention, a mask signal generator which outputs a mask signal having a predetermined bandwidth T1 in response to a signal leading edge and a signal trailing edge of the input signal, and said desired output signal is masked (disabled) with the mask signal, so that an output signal is always obtained a predetermined period (T1) after the input timing of the input signal.

摘要翻译： 在状态方案信号处理电路中，根据在输入信号的边缘的单触发脉冲电路输出的脉冲与状态信号之间的或信号获得期望的输出信号，由于输入信号和状态 信号彼此不同步，输出信号的输出定时根据输入信号的定时而改变。 因此，在本发明中，掩蔽信号发生器响应于输入信号的信号前沿和信号后沿输出具有预定带宽T1的屏蔽信号和所述期望输出信号被屏蔽（禁用） 掩模信号，使得在输入信号的输入定时之后总是获得预定周期（T1）的输出信号。

公开(公告)号：US20080278215A1

公开(公告)日：2008-11-13

申请号：US11860123

申请日：2007-09-24

申请人： Kenji Sakai ,  Yoshikazu Tanaka

发明人： Kenji Sakai ,  Yoshikazu Tanaka

IPC分类号： H03K17/28

CPC分类号： H02M1/08 ,  H03K17/162 ,  H03K17/284 ,  H03K17/6871 ,  H03K19/018507

摘要： A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals.

摘要翻译： 根据本发明的半导体器件是用于驱动和控制在高电位的主电源电位和主电源电位之间串联连接的两个功率器件的高电位侧的功率器件的半导体器件 低电位，并且配备有脉冲发生电路，用于产生对应于具有第一状态的第一和第二状态的第一和第二状态的电平转变的第一和第二脉冲信号，该第一状态具有示出高电位侧的功率器件的导通和 分别表示高电位侧的功率器件的非导通的第二状态; 电平移位电路，用于通过将第一和第二脉冲信号电平移位到高电位侧来获得第一和第二电平移位脉冲信号; 输入来自设定输入端的第一电平移位脉冲信号和来自复位输入端的第二电平移位脉冲信号的SR型触发电路; 以及用于将SR型触发器电路的输出至少延迟第一和第二脉冲信号的脉冲宽度的延迟电路。

公开(公告)号：US08174609B2

公开(公告)日：2012-05-08

申请号：US12454813

申请日：2009-05-22

申请人： Yoshihiro Sekimoto ,  Kazuya Fujita ,  Kiyoharu Shimano ,  Kenji Sakai

发明人： Yoshihiro Sekimoto ,  Kazuya Fujita ,  Kiyoharu Shimano ,  Kenji Sakai

IPC分类号： H04N5/235 ,  H04N5/225 ,  G03B7/00

CPC分类号： H04N5/2254 ,  H04N5/2257

摘要： In a camera module 1 of the present invention, a mechanical shutter 2 is provided above a top surface of a lens unit 3, and a protrusion section formed to an end of a lens 31 is held in a depression section formed on a back surface of the mechanical shutter 2. With the arrangement, it is possible to cause the camera module 1 employing the mechanical shutter 2 to be smaller and thinner at the same time.

摘要翻译： 在本发明的照相机模块1中，在透镜单元3的上表面的上方设置有机械挡板2，并且形成在透镜31的端部的突出部保持在形成在透镜单元3的背面的凹部 机械快门2.通过这种布置，可以使采用机械快门2的相机模块1同时变薄和变薄。

公开(公告)号：US20100072124A1

公开(公告)日：2010-03-25

申请号：US12442084

申请日：2007-09-12

申请人： Hirofumi Morikawa ,  Yuji Tanaka ,  Kenji Sakai ,  Hidetada Kobayashi

发明人： Hirofumi Morikawa ,  Yuji Tanaka ,  Kenji Sakai ,  Hidetada Kobayashi

IPC分类号： B01D63/04

CPC分类号： B01D63/022 ,  B01D63/02 ,  B01D2313/08 ,  B01D2313/20 ,  B01D2313/21

摘要： This invention provides a hollow fiber membrane module which can reduce pressure loss in discharging water within a module and can reduce operating power. A hollow fiber membrane bundle comprising a plurality of numbers of hollow fiber membranes are disposed within a cylindrical case having in its side face an opening part for the inflow/outflow of water, and the end of the hollow fiber membrane bundle is fixed by bonding at a position which is located in the axial direction of the cylindrical case at an outer position than the position of the opening part for the inflow/outflow of water on the side face of the cylindrical case. The hollow fiber membrane module is characterized in that a distribution cylinder provided with distribution holes is provided inward with respect to the opening part for the inflow/outflow of water on the side face of the cylindrical case and so as to surround the outer periphery of the hollow fiber membrane bundle, and grooves and/or corrugated protrusions are provided on the inner face of the distribution cylinder so as to be in communication with each other among the distribution holes.

摘要翻译： 本发明提供一种中空纤维膜组件，其可以减少在模块内排放水中的压力损失并且可以降低操作功率。 将包含多个中空纤维膜的中空纤维膜束设置在圆筒状的壳体内，其侧面具有用于水的流入/流出的开口部，中空纤维膜束的端部通过粘接固定在 位于圆柱形壳体的轴向方向上的位置，位于比用于在圆筒形壳体的侧面上的水的流入/流出的开口部的位置的外部位置。 中空纤维膜组件的特征在于，具有分配孔的分配筒相对于用于在圆筒形壳体的侧面上的水的流入/流出的开口部向内设置，以便围绕该圆筒形壳体的外周 中空纤维膜束，并且在分配筒的内表面上设置有槽和/或波纹状突起，以便在分配孔中彼此连通。