公开(公告)号：US07285831B2

公开(公告)日：2007-10-23

申请号：US11179434

申请日：2005-07-12

申请人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

发明人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

IPC分类号： H01L29/94

CPC分类号： H01L29/7846 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/7833 ,  H01L29/7843

摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

摘要翻译： 具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度 布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于 所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

公开(公告)号：US20060027876A1

公开(公告)日：2006-02-09

申请号：US11179434

申请日：2005-07-12

申请人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

发明人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/7846 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/7833 ,  H01L29/7843

摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

摘要翻译： 具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度 布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于 所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

公开(公告)号：US07179750B2

公开(公告)日：2007-02-20

申请号：US10685738

申请日：2003-10-15

申请人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

发明人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

IPC分类号： H01L21/302

CPC分类号： H01L29/42368 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/3185 ,  H01L27/11 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

公开(公告)号：US07323420B2

公开(公告)日：2008-01-29

申请号：US11652186

申请日：2007-01-11

申请人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

发明人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

IPC分类号： H01L21/302

CPC分类号： H01L29/42368 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/3185 ,  H01L27/11 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

摘要翻译： 在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。 使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。 选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。 选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。 此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。 结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分 。

公开(公告)号：US20070117391A1

公开(公告)日：2007-05-24

申请号：US11652186

申请日：2007-01-11

申请人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

发明人： Kyung-soo Kim ,  Young-wug Kim ,  Chang-bong Oh ,  Hee-sung Kang ,  Hyuk-ju Ryu

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L29/42368 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/3185 ,  H01L27/11 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

摘要翻译： 在制造半导体器件的多层栅极电介质层的方法中，在半导体衬底上形成第一介电层。 使用与构成第一电介质层上的第一电介质层的材料不同的电介质材料形成第二电介质层。 选择性地去除第二电介质层的一部分，以选择性地暴露第二介电层下的第一介电层。 选择性地去除暴露的第一介电层的一部分，以便在暴露的第一介电层下选择性地暴露半导体衬底。 此后，在暴露的半导体衬底上形成厚度比第一电介质层薄的第三电介质层。 结果，形成栅极电介质层，包括由第一电介质层和剩余的第二电介质层形成的厚部，由剩余的第一电介质层形成的中等厚度部分和由第三电介质层形成的薄壁部分 。

公开(公告)号：US07052965B2

公开(公告)日：2006-05-30

申请号：US10780245

申请日：2004-02-17

申请人： Chang-hyun Park ,  Young-gun Ko ,  Chang-bong Oh ,  Hee-sung Kang ,  Sang-jin Lee

发明人： Chang-hyun Park ,  Young-gun Ko ,  Chang-bong Oh ,  Hee-sung Kang ,  Sang-jin Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656

摘要： MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

摘要翻译： 制造具有袋区的MOSFET。 在半导体衬底上形成栅极电极层; 并且在与栅电极层相邻的半导体衬底中形成轻掺杂的漏极区。 在形成栅电极层的半导体衬底上形成阻挡图案。 阻挡图案与栅极电极层相邻并间隔预定距离，并且暴露半导体衬底的与栅极电极层的侧壁相邻的部分。 通过使用栅电极层和阻挡图案作为离子注入掩模注入杂质离子，在半导体衬底中形成口袋区域。

公开(公告)号：US06794716B2

公开(公告)日：2004-09-21

申请号：US09924787

申请日：2001-08-08

申请人： Sung-bae Park ,  Jun Kim ,  Eun-han Kim ,  Hee-sung Kang ,  Young-wug Kim

发明人： Sung-bae Park ,  Jun Kim ,  Eun-han Kim ,  Hee-sung Kang ,  Young-wug Kim

IPC分类号： H01L2701

CPC分类号： H01L29/78615 ,  H01L29/78612

摘要： An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.

摘要翻译： 提供了具有用于防止浮体效应的身体接触的SOI MOSFET。 身体接触是将半体衬底穿孔的沟槽和掩埋氧化物层。 沟槽填充有导电材料以将本体电连接到半导体衬底。 将杂质离子注入到与身体接触的下部接触的半导体衬底的预定区域中以形成欧姆接触。 在SOI MOSFET中，不需要额外的金属互连线来为电源供电。 此外，可以防止由于接触的杂散电容引起的电路故障。