公开(公告)号：US07105900B2

公开(公告)日：2006-09-12

申请号：US10388353

申请日：2003-03-13

申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。

公开(公告)号：US06498370B1

公开(公告)日：2002-12-24

申请号：US09695341

申请日：2000-10-24

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

IPC分类号： H01L2701

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

摘要翻译： 提供绝缘体上硅（SOD集成电路和制造SOI集成电路的方法），在SOI衬底上形成至少一个隔离晶体管有源区和体线，晶体管有源区和体线被包围 通过与SOI衬底的埋置绝缘层接触的隔离层，将晶体管有源区的侧壁的一部分延伸到体线，由此，晶体管有源区域通过a 主体延伸部由主体绝缘层覆盖，在晶体管有源区域上形成绝缘栅极图案，栅极图案的一端与主体绝缘层重叠。

公开(公告)号：US06492260B1

公开(公告)日：2002-12-10

申请号：US09447466

申请日：1999-11-22

申请人： Young-wug Kim ,  Kyung-tae Lee

发明人： Young-wug Kim ,  Kyung-tae Lee

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/76834

摘要： A method of forming damascene wiring without dishing and erosion employs a dummy layer to slow or delay polishing in selected regions and thereby prevent dishing and erosion of the damascene wiring. The dummy layer is above wide damascene regions and areas containing closely packed damascene regions. Therefore, non-uniform sheet resistance of the damascene metal wiring and electro-migration due to an increase in the local current density of the metal wiring can be prevented.

摘要翻译： 在不进行凹陷和侵蚀的情况下形成镶嵌布线的方法使用虚拟层来减缓或延迟所选区域中的抛光，从而防止镶嵌布线的凹陷和侵蚀。 虚拟层位于宽大的镶嵌区域和包含紧密堆积的镶嵌区域的区域之上。 因此，可以防止由金属布线的局部电流密度的增加引起的非镶嵌金属布线的非均匀的薄层电阻和电迁移。

公开(公告)号：US5674782A

公开(公告)日：1997-10-07

申请号：US611432

申请日：1996-03-04

申请人： Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

发明人： Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213

CPC分类号： H01L21/02071 ,  H01L21/28061 ,  H01L21/32135

摘要： A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.

摘要翻译： 一种用于有效地除去在干法蚀刻半导体器件，特别是多晶硅化物结构的制造结构中产生的副产物的方法。 该方法包括以下步骤：顺序地形成多晶硅层和难熔金属硅化物层以覆盖半导体衬底上先前制造的结构，干蚀刻多晶硅层和难熔金属硅化物层以形成图案化的多晶硅层和图案化的难熔金属 硅化物层，并对所得结构进行热处理，以在高于任何副产物的沸点的温度下除去在干蚀刻步骤中产生的至少一种副产物。

公开(公告)号：US07602465B2

公开(公告)日：2009-10-13

申请号：US10695396

申请日：2003-10-29

申请人： Kyong Seok Kim ,  Young Wug Kim

发明人： Kyong Seok Kim ,  Young Wug Kim

IPC分类号： G02F1/1343

CPC分类号： G09G3/3688 ,  G02F1/134363 ,  G02F1/136213 ,  G02F1/1368 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2310/027 ,  G09G2310/0289

摘要： An In-Plane switching mode LCD device includes a plurality of gate and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistor (TFT) formed at crossing points of the gate and data lines to be alternately positioned along lower and upper side pixel regions adjacent to corresponding gate lines, a plurality of storage lines disposed in an offset configuration to be parallel with the gate lines along the TFT regions, a plurality of pixel electrodes within the pixel regions to be connected to drain electrodes of the TFTs, and a plurality of common electrodes disposed at fixed intervals from the pixel electrodes to be connected to the storage lines.

摘要翻译： 平面切换模式LCD装置包括彼此交叉以形成多个像素区域的多个栅极和数据线，形成在栅极和数据线的交叉点处以交替定位的多个薄膜晶体管（TFT） 沿着与对应的栅极线相邻的下侧和上侧像素区域，沿着TFT区域设置成与栅极线平行的偏移配置的多个存储线，要连接到漏电极的像素区域内的多个像素电极 的TFT，以及从像素电极以固定的间隔设置的多个公共电极连接到存储线。

公开(公告)号：US06911397B2

公开(公告)日：2005-06-28

申请号：US10412522

申请日：2003-04-11

申请人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

发明人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

摘要翻译： 形成双镶嵌互连的方法采用低k介电有机聚合物作为绝缘层。 仅使用一个硬掩模层，使用与自对准间隔物的蚀刻速率不同的硬掩模层和蚀刻停止层来防止对绝缘层的灰化损伤。 此外，可以形成小于光刻工艺的分辨率极限的通孔。 结果，该过程被简化，并且不发生光致抗蚀剂尾部现象。

公开(公告)号：US06794716B2

公开(公告)日：2004-09-21

申请号：US09924787

申请日：2001-08-08

申请人： Sung-bae Park ,  Jun Kim ,  Eun-han Kim ,  Hee-sung Kang ,  Young-wug Kim

发明人： Sung-bae Park ,  Jun Kim ,  Eun-han Kim ,  Hee-sung Kang ,  Young-wug Kim

IPC分类号： H01L2701

CPC分类号： H01L29/78615 ,  H01L29/78612

摘要： An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.

摘要翻译： 提供了具有用于防止浮体效应的身体接触的SOI MOSFET。 身体接触是将半体衬底穿孔的沟槽和掩埋氧化物层。 沟槽填充有导电材料以将本体电连接到半导体衬底。 将杂质离子注入到与身体接触的下部接触的半导体衬底的预定区域中以形成欧姆接触。 在SOI MOSFET中，不需要额外的金属互连线来为电源供电。 此外，可以防止由于接触的杂散电容引起的电路故障。

公开(公告)号：US06689648B2

公开(公告)日：2004-02-10

申请号：US10134798

申请日：2002-04-29

申请人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

IPC分类号： H01L2100

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

摘要翻译： SOI半导体器件及SOI半导体器件的制造方法本发明涉及一种SOI半导体器件的制造方法，其中由硅化物层形成的部分在隔离层中被横向限制在用于二极管或阱电阻器的扩散区域中的预定范围内。 以这种方式，可以固定硅化物层和扩散区域的侧面之间的距离长度，大于现有技术中可用的距离，从而最小化扩散区域侧面的功率泄漏。 在如此构造的SOI半导体器件中，用于二极管（或阱电阻器）的扩散区域由具有不同密度杂质层的双结结构中的间隔物构成（例如，P-或N-层分别围绕 P +或N +层），换句话说，仅在高密度的杂​​质层，P +或N +层上，或在单结结构中，其中间隔物限制在扩散区域中形成硅化物层的空间范围。

公开(公告)号：US06255697B1

公开(公告)日：2001-07-03

申请号：US09343997

申请日：1999-06-30

申请人： Kwang-dong Yoo ,  Young-wug Kim ,  Seok-kyun Jung

发明人： Kwang-dong Yoo ,  Young-wug Kim ,  Seok-kyun Jung

IPC分类号： H01L2976

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76819 ,  H01L21/76885 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions. The plurality of dummy conductive regions are formed on the node regions of the lattice-shaped isolation region. In another embodiment, an array of isolation regions is formed, defining a lattice-shaped dummy active region. An array of dummy conductive regions is formed on the array of isolation regions. Related integrated circuit devices are also described.

摘要翻译： 通过在诸如单片半导体衬底或绝缘体上硅（SOI））衬底的半导体衬底的区域中形成至少一个隔离区域来制造集成电路器件。 所述至少一个隔离区域限定至少一个活性区域。 多个虚设导电区域分布在半导体衬底的区域中，其中虚拟导电区域被限制为覆盖至少一个隔离区域。 虚拟导电区域可以由也用于形成例如栅电极，电容器电极或布线图案的导电层形成。 虚拟导电区域可以形成在绝缘层上，例如栅极绝缘层或层间电介质层。 优选地，虚拟导电区域是不连续的。 在一个实施例中，形成格子状隔离区域，其包括通过互连区域链接并限定虚拟活动区域阵列的节点区域阵列。 多个虚设导电区域形成在格子状隔离区域的节点区域上。 在另一个实施例中，形成隔离区域阵列，限定了格状的虚拟有源区域。 在隔离区域阵列上形成一个虚拟导电区域阵列。 还描述了相关的集成电路器件。

公开(公告)号：US07410843B2

公开(公告)日：2008-08-12

申请号：US11428911

申请日：2006-07-06

申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

IPC分类号： H01L21/84

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。