公开(公告)号：US20180151297A1

公开(公告)日：2018-05-31

申请号：US15864534

申请日：2018-01-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： KAZUO HATTORI ,  Noriyuki Inoue ,  Hiromasa Saeki ,  Kensuke Aoki ,  Ken Ito

IPC: H01G4/12 ,  H01G4/33 ,  H01G4/38 ,  H01G4/005 ,  H01G9/045 ,  H01G9/055 ,  H01G9/07

CPC classification number: H01G4/12 ,  H01G4/005 ,  H01G4/33 ,  H01G4/38 ,  H01G9/012 ,  H01G9/0425 ,  H01G9/045 ,  H01G9/055 ,  H01G9/07 ,  H01G9/15

Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.

公开(公告)号：US20180047517A1

公开(公告)日：2018-02-15

申请号：US15725652

申请日：2017-10-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： KOICHI KANRYO ,  Noriyuki Inoue ,  Hiromasa Saeki ,  Takeo Arakawa ,  Kazuo Hattori ,  Ken Ito

IPC: H01G9/15 ,  H01G4/12 ,  H01G4/33 ,  H01G9/028 ,  H01G9/012 ,  H01G9/26 ,  H01G9/00 ,  H01G4/10 ,  H01L49/02

CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G4/12 ,  H01G4/33 ,  H01G9/0032 ,  H01G9/0036 ,  H01G9/012 ,  H01G9/028 ,  H01G9/26 ,  H01L28/75 ,  H01L28/84

Abstract: A capacitor that includes a conductive metal base material with a porous part, a dielectric layer on the porous part, and an upper electrode on the dielectric layer, and has an electrostatic capacitance formation part only on one principal surface side of the capacitor.

公开(公告)号：US09865400B2

公开(公告)日：2018-01-09

申请号：US15204069

申请日：2016-07-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ken Ito ,  Noriyuki Inoue ,  Koichi Kanryo

IPC: H01G9/07 ,  H01G9/042 ,  H01G9/055 ,  H01G9/045

CPC classification number: H01G9/07 ,  H01G9/0029 ,  H01G9/042 ,  H01G9/045 ,  H01G9/055

Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 μm or more at ½ of a depth of the at least one groove.

公开(公告)号：US10658111B2

公开(公告)日：2020-05-19

申请号：US15864534

申请日：2018-01-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo Hattori ,  Noriyuki Inoue ,  Hiromasa Saeki ,  Kensuke Aoki ,  Ken Ito

IPC: H01G4/33 ,  H01G4/38 ,  H01G4/005 ,  H01G9/045 ,  H01G9/055 ,  H01G9/07 ,  H01G9/042 ,  H01G9/15 ,  H01G9/012

Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.

公开(公告)号：US20170018368A1

公开(公告)日：2017-01-19

申请号：US15204069

申请日：2016-07-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ken Ito ,  Noriyuki Inoue ,  Koichi Kanryo

IPC: H01G9/07 ,  H01G9/055 ,  H01G9/042

CPC classification number: H01G9/07 ,  H01G9/0029 ,  H01G9/042 ,  H01G9/045 ,  H01G9/055

Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 μm or more at ½ of a depth of the at least one groove.

Abstract translation: 一种电容器，包括导电多孔基材; 电介质层; 和电极。 导电性多孔基材，电介质层和上电极层叠在一起，构成在导电性多孔质基材与电极之间施加电压时在电介质层中蓄积电荷的有效部。 导电性多孔基材包括在至少一个凹槽的深度的1/2处具有10μm以上的宽度的至少一个凹槽。