公开(公告)号：US10727295B2

公开(公告)日：2020-07-28

申请号：US16176506

申请日：2018-10-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tatsuya Funaki ,  Noriyuki Inoue

IPC: H01L29/00 ,  H01L49/02 ,  H01G4/33 ,  H01G4/12 ,  H01L21/56 ,  H01L23/525 ,  H01L23/522 ,  H01L23/00 ,  H01L23/12 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.

公开(公告)号：US20170076872A1

公开(公告)日：2017-03-16

申请号：US15363336

申请日：2016-11-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： TAKEO ARAKAWA ,  Hiromasa Saeki ,  Noriyuki Inoue ,  Naoki Iwaji

IPC: H01G9/045 ,  H01G9/00 ,  H01G9/048 ,  H01G9/15

CPC classification number: H01G9/045 ,  H01G9/0032 ,  H01G9/0036 ,  H01G9/048 ,  H01G9/055 ,  H01G9/07 ,  H01G9/15

Abstract: A capacitor that includes a porous metallic base material; a phosphorus-containing layer on the porous metallic base material; a dielectric layer on the phosphorus-containing layer; and an electrode on the dielectric layer.

Abstract translation: 一种电容器，包括多孔金属基材; 多孔金属基材上的含磷层; 含磷层上的介电层; 和电介质层上的电极。

公开(公告)号：US09153382B2

公开(公告)日：2015-10-06

申请号：US13936410

申请日：2013-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takafumi Okamoto ,  Noriyuki Inoue

IPC: H01G4/06 ,  C04B35/00 ,  H01G4/12 ,  C01G23/00 ,  C01G25/00 ,  C04B35/468 ,  C04B35/49 ,  H01B3/12 ,  H01G4/30

CPC classification number: H01G4/1209 ,  C01G23/006 ,  C01G25/006 ,  C01P2002/34 ,  C01P2002/50 ,  C01P2006/40 ,  C04B35/4682 ,  C04B35/49 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3262 ,  C04B2235/3418 ,  C04B2235/652 ,  C04B2235/6582 ,  C04B2235/6584 ,  C04B2235/6588 ,  H01B3/12 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor exhibits superior life characteristics in a high temperature load test despite the use of very thin dielectric layers. As a dielectric ceramic constituting a dielectric layer of the multilayer ceramic capacitor, a perovskite-type compound is used and contains Ba and Ti (a portion of Ba can be replaced with at least one of Ca and Sr, and a portion of Ti can be replaced with Zr) as a main component, and including La within the range of 2-6 parts by mole, Mg within the range of 3-5 parts by mole, and Mn within the range of 1.5-3 parts by mole in a case where a total content of Ti and Zr is 100 parts by mole.

Abstract translation: 尽管使用非常薄的电介质层，但是在高温负载测试中，多层陶瓷电容器具有优异的寿命特性。 作为构成多层陶瓷电容器的电介质层的电介质陶瓷，使用钙钛矿型化合物，含有Ba和Ti（Ba的一部分可以用Ca和Sr中的至少一种代替，Ti的一部分可以 以Zr为主成分），其中La为2-6摩尔％，Mg为3-5摩尔％，Mn为1.5〜3摩尔的范围， 其中Ti和Zr的总含量为100份摩尔。

公开(公告)号：US10658111B2

公开(公告)日：2020-05-19

申请号：US15864534

申请日：2018-01-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo Hattori ,  Noriyuki Inoue ,  Hiromasa Saeki ,  Kensuke Aoki ,  Ken Ito

IPC: H01G4/33 ,  H01G4/38 ,  H01G4/005 ,  H01G9/045 ,  H01G9/055 ,  H01G9/07 ,  H01G9/042 ,  H01G9/15 ,  H01G9/012

Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.

公开(公告)号：US10256045B2

公开(公告)日：2019-04-09

申请号：US15209128

申请日：2016-07-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromasa Saeki ,  Noriyuki Inoue ,  Takeo Arakawa ,  Naoki Iwaji

IPC: H01G9/032 ,  H01G9/07 ,  H01G9/00 ,  H01G9/055 ,  H01G9/15 ,  H01G9/04 ,  H01G9/045 ,  H01G9/052

Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.

公开(公告)号：US20170018368A1

公开(公告)日：2017-01-19

申请号：US15204069

申请日：2016-07-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ken Ito ,  Noriyuki Inoue ,  Koichi Kanryo

IPC: H01G9/07 ,  H01G9/055 ,  H01G9/042

CPC classification number: H01G9/07 ,  H01G9/0029 ,  H01G9/042 ,  H01G9/045 ,  H01G9/055

Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 μm or more at ½ of a depth of the at least one groove.

Abstract translation: 一种电容器，包括导电多孔基材; 电介质层; 和电极。 导电性多孔基材，电介质层和上电极层叠在一起，构成在导电性多孔质基材与电极之间施加电压时在电介质层中蓄积电荷的有效部。 导电性多孔基材包括在至少一个凹槽的深度的1/2处具有10μm以上的宽度的至少一个凹槽。

公开(公告)号：US20160329158A1

公开(公告)日：2016-11-10

申请号：US15213684

申请日：2016-07-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： KAZUO HATTORI ,  Noriyuki Inoue ,  Takeo Arakawa ,  Hiromasa Saeki

IPC: H01G9/15 ,  H01G9/00 ,  H01G9/012 ,  H01G9/07 ,  H01G9/055 ,  H01G9/045

CPC classification number: H01G9/15 ,  H01G9/0032 ,  H01G9/012 ,  H01G9/04 ,  H01G9/045 ,  H01G9/048 ,  H01G9/055 ,  H01G9/07

Abstract: A capacitor that includes a porous metal base material, a dielectric layer formed on the porous metal base material, an upper electrode formed on the dielectric layer, a first terminal electrode electrically connected to the porous metal base material, and a second terminal electrode electrically connected to the upper electrode. The porous metal base material includes a high-porosity part and low-porosity parts, and the low-porosity parts are present at a pair of opposed side surfaces of the porous metal base material.

Abstract translation: 一种电容器，包括多孔金属基材，形成在所述多孔金属基材上的电介质层，形成在所述电介质层上的上电极，与所述多孔金属基材电连接的第一端电极和电连接的第二端电极 到上电极。 多孔金属基材包括高孔隙率部分和低孔隙率部分，并且低孔隙率部分存在于多孔金属基材的一对相对的侧表面。

公开(公告)号：US11348726B2

公开(公告)日：2022-05-31

申请号：US16527170

申请日：2019-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takehito Ishihara ,  Noriyuki Inoue ,  Tatsuya Funaki

IPC: H01G4/005 ,  H01G4/33 ,  H01G9/07 ,  H01L49/02

Abstract: A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.

公开(公告)号：US10186383B2

公开(公告)日：2019-01-22

申请号：US15213684

申请日：2016-07-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo Hattori ,  Noriyuki Inoue ,  Takeo Arakawa ,  Hiromasa Saeki

IPC: H01G9/15 ,  H01G9/04 ,  H01G9/055 ,  H01G9/012 ,  H01G9/048 ,  H01G9/00 ,  H01G9/045 ,  H01G9/07

Abstract: A capacitor that includes a porous metal base material, a dielectric layer formed on the porous metal base material, an upper electrode formed on the dielectric layer, a first terminal electrode electrically connected to the porous metal base material, and a second terminal electrode electrically connected to the upper electrode. The porous metal base material includes a high-porosity part and low-porosity parts, and the low-porosity parts are present at a pair of opposed side surfaces of the porous metal base material.

公开(公告)号：US20180174760A1

公开(公告)日：2018-06-21

申请号：US15846626

申请日：2017-12-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： KAZUO HATTORI ,  Noriyuki Inoue

IPC: H01G9/045 ,  H01G9/15 ,  H01G9/07 ,  H01G9/055 ,  H01G4/012 ,  H01G4/33 ,  H01G4/12 ,  H01G4/08 ,  H01G9/012

CPC classification number: H01G9/045 ,  H01G4/085 ,  H01G4/10 ,  H01G4/12 ,  H01G4/1272 ,  H01G4/28 ,  H01G4/33 ,  H01G9/012 ,  H01G9/055 ,  H01G9/07 ,  H01G9/15

Abstract: A capacitor includes a first electrode formed from a conductive porous base material, a dielectric layer located on the first electrode and a second electrode located on the dielectric layer. The first electrode is electrically connected to first and second terminal electrodes located on respective opposite ends of the first electrode. The second electrode is located between the first and second terminal electrodes and is electrically connected to a third terminal electrode located on the second electrode.