公开(公告)号：US11949003B2

公开(公告)日：2024-04-02

申请号：US17714860

申请日：2022-04-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Isao Obu ,  Kaoru Ideno ,  Shigeki Koya

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/0692 ,  H01L29/0817

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US11705509B2

公开(公告)日：2023-07-18

申请号：US16992067

申请日：2020-08-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H03F3/21

CPC classification number: H01L29/7371 ,  H01L21/28575 ,  H01L21/308 ,  H01L21/30612 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/0817 ,  H01L29/0826 ,  H03F3/21

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US11508835B2

公开(公告)日：2022-11-22

申请号：US17569494

申请日：2022-01-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

公开(公告)号：US11289434B2

公开(公告)日：2022-03-29

申请号：US16904775

申请日：2020-06-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Yasunari Umemoto ,  Isao Obu ,  Masao Kondo ,  Yuichi Saito ,  Takayuki Tsutsui

IPC: H01L23/66 ,  H01L23/00 ,  H03F3/195

Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.

公开(公告)号：US11251290B2

公开(公告)日：2022-02-15

申请号：US17229564

申请日：2021-04-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

公开(公告)号：US10964693B2

公开(公告)日：2021-03-30

申请号：US16440700

申请日：2019-06-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Shigeki Koya ,  Yasunari Umemoto ,  Takayuki Tsutsui

IPC: H01L27/082 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498 ,  H01L21/8252 ,  H03F3/20 ,  H03F1/56

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

公开(公告)号：US10903803B2

公开(公告)日：2021-01-26

申请号：US16785482

申请日：2020-02-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Kenichi Nagura

IPC: H01L29/06 ,  H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/16 ,  H01L21/8252

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US10778159B2

公开(公告)日：2020-09-15

申请号：US16192890

申请日：2018-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Satoshi Tanaka ,  Takayuki Tsutsui ,  Yasunari Umemoto

IPC: H03F3/21 ,  H01L21/82 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06 ,  H01L21/8252

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US10541320B2

公开(公告)日：2020-01-21

申请号：US16375724

申请日：2019-04-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L21/00 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

公开(公告)号：US10147809B2

公开(公告)日：2018-12-04

申请号：US14988016

申请日：2016-01-05

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari Umemoto ,  Atsushi Kurokawa ,  Tsunekazu Saimei

IPC: H01L29/737 ,  H01L29/36 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/12

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.