公开(公告)号：US11631758B2

公开(公告)日：2023-04-18

申请号：US16810492

申请日：2020-03-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Isao Obu ,  Kaoru Ideno ,  Shigeki Koya

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/737

Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

公开(公告)号：US11476807B2

公开(公告)日：2022-10-18

申请号：US17082990

申请日：2020-10-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Takayuki Tsutsui ,  Yasunari Umemoto ,  Isao Obu ,  Satoshi Tanaka

IPC: H03F1/32 ,  H03F3/21 ,  H03F3/19 ,  H03G3/00 ,  H03F1/56 ,  H03F1/02 ,  H03G3/30 ,  H03F3/24

Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.

公开(公告)号：US10957617B2

公开(公告)日：2021-03-23

申请号：US16374674

申请日：2019-04-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Isao Obu ,  Yasunari Umemoto ,  Yasuhisa Yamamoto ,  Masahiro Shibata ,  Takayuki Tsutsui

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H03F1/30 ,  H03F3/68

Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.

公开(公告)号：US10886388B2

公开(公告)日：2021-01-05

申请号：US16822889

申请日：2020-03-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/205

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US10777669B2

公开(公告)日：2020-09-15

申请号：US16152285

申请日：2018-10-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H03F3/21

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US10475717B2

公开(公告)日：2019-11-12

申请号：US15899010

申请日：2018-02-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata

IPC: H01L21/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/67 ,  H01L21/56 ,  H01L21/52 ,  H01L23/48 ,  H01L23/498 ,  H01L21/683 ,  H01L21/768 ,  H01L23/367

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

公开(公告)号：US09859405B1

公开(公告)日：2018-01-02

申请号：US15610711

申请日：2017-06-01

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Shigeru Yoshida ,  Masahiro Shibata

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/737 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/12 ,  H01L29/20 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.

公开(公告)号：US11817356B2

公开(公告)日：2023-11-14

申请号：US17559958

申请日：2021-12-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu ,  Kaoru Ideno

IPC: H01L29/66 ,  H01L21/8252 ,  H01L29/737 ,  H01L29/15

CPC classification number: H01L21/8252 ,  H01L29/157 ,  H01L29/66333 ,  H01L29/7371

Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.

公开(公告)号：US11735541B2

公开(公告)日：2023-08-22

申请号：US16452637

申请日：2019-06-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya Kobayashi ,  Atsushi Kurokawa ,  Hiroaki Tokuya ,  Isao Obu ,  Yuichi Saito

IPC: H01L23/31 ,  H01L23/00 ,  H01L49/02 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L27/0658 ,  H01L27/0664 ,  H01L27/0676 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/04105 ,  H01L2224/05558 ,  H01L2224/05573

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

公开(公告)号：US11658180B2

公开(公告)日：2023-05-23

申请号：US17188961

申请日：2021-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Shigeki Koya ,  Yasunari Umemoto ,  Takayuki Tsutsui

IPC: H01L27/082 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498 ,  H01L21/8252 ,  H03F3/20 ,  H03F1/56

CPC classification number: H01L27/0823 ,  H01L21/8252 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/7304 ,  H01L29/7371 ,  H01L2223/6655 ,  H01L2224/11462 ,  H01L2224/13019 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/16227 ,  H01L2224/81815 ,  H03F1/56 ,  H03F3/20 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.