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公开(公告)号：US20070291851A1
公开(公告)日：2007-12-20
申请号：US11454410
申请日：2006-06-16
IPC分类号： H04N7/12
摘要： Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.
摘要翻译： 公开了用于硬件加速的压缩视频比特流转义码处理的装置，系统和方法，包括包括用于解析压缩视频数据的比特流的比特流解析器（BSP）的装置。 BSP包括当BSP在比特流中检测到转义码时从比特流提取未压缩运行和电平数据的电路。 公开了其他实现。
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公开(公告)号：US20140098888A1
公开(公告)日：2014-04-10
申请号：US14102576
申请日：2013-12-11
IPC分类号： H04N7/26
摘要： Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.
摘要翻译： 公开了用于硬件加速的压缩视频比特流转义码处理的装置，系统和方法，包括包括用于解析压缩视频数据的比特流的比特流解析器（BSP）的装置。 BSP包括当BSP在比特流中检测到转义码时从比特流提取未压缩运行和电平数据的电路。 公开了其他实现。
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公开(公告)号：US08630354B2
公开(公告)日：2014-01-14
申请号：US11454410
申请日：2006-06-16
IPC分类号： H04N7/12
摘要： Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.
摘要翻译： 公开了用于硬件加速的压缩视频比特流转义码处理的装置，系统和方法，包括包括用于解析压缩视频数据的比特流的比特流解析器（BSP）的装置。 BSP包括当BSP在比特流中检测到转义码时从比特流提取未压缩运行和电平数据的电路。 公开了其他实现。
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4.发明授权Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design 有权在混合语言混合信号设计中连接verilog-AMS和VHDL-AMS组件公开(公告)号：US07251795B2
公开(公告)日：2007-07-31
申请号：US10952222
申请日：2004-09-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.
摘要翻译： 在混合语言混合信号设计中连接Verilog-AMS和VHDL-AMS组件的方法包括接收混合语言混合信号设计，其中混合语言混合信号设计包括一个或多个VHDL-AMS和Verilog -AMS组件，包括第一个VHDL-AMS组件和第一个Verilog-AMS组件。 该方法还包括接收一组预定的连接规则，根据预定的连接规则集解决第一VHDL-AMS组件与第一Verilog-AMS组件之间的不兼容性，并将第一VHDL-AMS组件连接到第一个Verilog -AMS组件。
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5.发明申请Processor architecture for executing two different fixed-length instruction sets 审中-公开用于执行两个不同固定长度指令集的处理器架构公开(公告)号：US20050262329A1
公开(公告)日：2005-11-24
申请号：US10644226
申请日：2003-08-19
申请人： Sivaram Krishnan , Mark Debbage , Sebastian Ziesler , Kanad Roy , Andrew Sturges , Prasenjit Biswas
发明人： Sivaram Krishnan , Mark Debbage , Sebastian Ziesler , Kanad Roy , Andrew Sturges , Prasenjit Biswas
CPC分类号： G06F9/30174
摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is accomplished by branch instructions that employ a least significant bit position of the address of the target of the branch to identify whether the target instruction is a 16-bit instruction or a 32-bit instruction.
摘要翻译： 构造为执行32位固定长度指令集架构的处理器元件通过将16位指令中的每一个转换成一个或多个32位指令的序列而与16位固定长度指令集架构向后兼容 。 在16位指令执行和32位指令执行之间进行切换是通过使用分支目标地址的最低有效位位置的分支指令来实现的，以识别目标指令是16位指令还是32位指令， 位指令。
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公开(公告)号：US20130202041A1
公开(公告)日：2013-08-08
申请号：US13744921
申请日：2013-01-18
申请人： Yi-jen Chiu , MEI-CHEN YEH , Prasenjit Biswas , Louis Lippincott
发明人： Yi-jen Chiu , MEI-CHEN YEH , Prasenjit Biswas , Louis Lippincott
IPC分类号： H04N7/26
CPC分类号： H04N19/51 , H04N19/112 , H04N19/186 , H04N19/513 , H04N19/573
摘要： A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter. Other embodiments are described and claimed.
摘要翻译： 描述了用于处理色度运动矢量的系统，装置，方法和物品。 该装置可以包括视频解码器。 视频解码器包括用于接收压缩视频比特流的处理器。 压缩视频比特流包括图像流。 图像流包括切片内的当前切片和当前块。 处理器预先计算当前切片的色度运动矢量调整参数，并使用预先计算的色度运动矢量调整参数确定当前切片内当前块的运动矢量分量。 描述和要求保护其他实施例。
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公开(公告)号：US20060259879A1
公开(公告)日：2006-11-16
申请号：US11126497
申请日：2005-05-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/505 , G06F2217/86
摘要： A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.
摘要翻译： 公开了一种混合语言和混合信号（MLMS）设计建模方法。 该方法包括接收MLMS设计，该MLMS设计包括至少数字驱动器，数字接收器和由分层结构中的MLMS网连接的模拟块，并且识别MLMS设计的模拟数字边界。 对于每个模拟数字边界，该方法还包括：a）通过使用预定的纪律解决程序来选择连接模块（CM）; b）确定CM的输入驱动值; 以及c）将数字驱动器，数字接收器和模拟块连接到CM。 该方法在MLMS设计的所有模拟 - 数字边界上重复步骤a），b）和c）。
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公开(公告)号：US06418528B1
公开(公告)日：2002-07-09
申请号：US09131881
申请日：1998-08-10
IPC分类号： G06F9302
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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公开(公告)号：US5860000A
公开(公告)日：1999-01-12
申请号：US594763
申请日：1996-01-31
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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10.发明申请FLEXIBLE MACROBLOCK ORDERING AND ARBITRARY SLICE ORDERING APPARATUS, SYSTEM, AND METHOD 有权灵活的宏块订单和仲裁订单设备，系统和方法公开(公告)号：US20120134418A1
公开(公告)日：2012-05-31
申请号：US13367449
申请日：2012-02-07
申请人： Yi-Jen Chiu , Prasenjit Biswas
发明人： Yi-Jen Chiu , Prasenjit Biswas
CPC分类号： H04N19/44 , H04N19/112 , H04N19/129 , H04N19/174 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/61 , H04N19/70
摘要： A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.
摘要翻译： 描述了处理柔性宏块排序和任意片排序的系统，装置，方法和制品。 该装置可以包括视频解码器。 视频解码器包括处理器，用于存储数据缓冲器中的一个或多个相邻宏块的编码参数。 相邻宏块是先前解码的宏块，并且与当前宏块相邻。 处理器用于存储数据缓冲器中的一个或多个相邻宏块中的每一个的控制参数。 处理器使用与相邻宏块相关联的可用性信息来重构当前宏块的编码参数。
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