公开(公告)号：US06437380B1

公开(公告)日：2002-08-20

申请号：US09819542

申请日：2001-03-28

申请人： Myoungho Lim ,  Vikram Joshi ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

发明人： Myoungho Lim ,  Vikram Joshi ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

IPC分类号： H01L2976

CPC分类号： H01L29/516 ,  H01L28/56

摘要： An integrated circuit device includes a thin film of bismuth-containing layered superlattice material having a thickness not exceeding 100 nm, a capping layer thin film of bismuth tantalate, and an electrode. The capping layer has a thickness in a range of from 3 nm to 30 nm and is deposited between the thin film of layered superlattice material and the electrode to increase dielectric breakdown voltage. Preferably the capping layer contains an excess amount of bismuth relative to the stoichiometrically balanced amount represented by the balanced stoichiometric formula BiTaO4. Preferably, the layered superlattice material is ferroelectric SBT or SBTN. Preferably, the integrated circuit device is a nonvolatile ferroelectric memory. Heating treatments for fabrication of the integrated circuit device containing the bismuth tantalate capping layerare conducted at temperatures not exceeding 700° C., preferably in a range of from 650° C. to 700° C.

摘要翻译： 集成电路器件包括厚度不超过100nm的含铋层状超晶格材料薄膜，钽酸铋覆盖层薄膜和电极。 覆盖层的厚度在3nm至30nm的范围内，并且沉积在层状超晶格材料的薄膜和电极之间以增加介电击穿电压。 优选地，封盖层相对于由平衡化学计量式BiTaO 4表示的化学计量平衡量含有过量的铋。 优选地，层状超晶格材料是铁电SBT或SBTN。 优选地，集成电路器件是非易失性铁电存储器。 用于制造包含钽酸铋覆盖层的集成电路器件的加热处理在不超过700℃的温度下进行，优选在650℃至700℃的范围内。

公开(公告)号：US06815223B2

公开(公告)日：2004-11-09

申请号：US10302441

申请日：2002-11-22

申请人： Jolanta Celinska ,  Vikram Joshi ,  Narayan Solayappan ,  Myoungho Lim ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

发明人： Jolanta Celinska ,  Vikram Joshi ,  Narayan Solayappan ,  Myoungho Lim ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

IPC分类号： H01G706

CPC分类号： H01L28/55 ,  C30B29/32 ,  C30B29/68

摘要： A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.-sec, preferably less than 50,000° C.-sec.

公开(公告)号：US06339238B1

公开(公告)日：2002-01-15

申请号：US09329670

申请日：1999-06-10

申请人： Myoungho Lim ,  Vikram Joshi ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

发明人： Myoungho Lim ,  Vikram Joshi ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

IPC分类号： H01L2972

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/0629 ,  H01L29/78391

摘要： A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.

摘要翻译： 一种铁电非易失性存储器，其中每个存储单元由单个电子元件，铁电FET组成。 FET包括源极，漏极，栅极和衬底。 通过对源极，漏极，栅极或衬底施加偏置电压来选择单元进行写入或读取。 通过行解码器施加等于一个真值表逻辑值的栅极电压和等于另一个真值表逻辑值的漏极电压，经由列解码器施加等于第三真值表逻辑值的衬底偏置以写入 记录结果Ids逻辑状态，通过在源极和漏极之间放置电压可以非破坏性地读取。

公开(公告)号：US06441414B1

公开(公告)日：2002-08-27

申请号：US09170590

申请日：1998-10-13

申请人： Myoungho Lim ,  Vikram Joshi ,  Jeffrey W. Bacon ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

发明人： Myoungho Lim ,  Vikram Joshi ,  Jeffrey W. Bacon ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L29/78391

摘要： A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. The fact that the drain to source current, lds, is always negative if a substrate to drain bias, Vss, of 0.8 volts or more is applied, permits the creation of a read and write truth table. A gate voltage equal to one truth table logic value is applied via a column decoder and a substrate bias equal to another truth table logic value is applied via a row decoder to write to the memory a resultant lds logic state, which can be read whenever a voltage is placed across the source and drain.

摘要翻译： 一种铁电非易失性存储器，其中每个存储单元由单个电子元件，铁电FET组成。 FET包括源极，漏极，栅极和衬底。 如果施加0.8伏或更高的衬底到漏极偏压Vss，则漏源到源电流lds总是为负，这允许创建读写真值表。 通过列解码器施加等于一个真值表逻辑值的栅极电压，并且经由行解码器施加等于另一个真值表逻辑值的衬底偏置，以向存储器写入结果lds逻辑状态，其可以在每当 电压跨过源极和漏极放置。

公开(公告)号：US06924997B2

公开(公告)日：2005-08-02

申请号：US10381235

申请日：2001-09-25

申请人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

发明人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

摘要翻译： 铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息 放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等） 驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。 通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。 在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

公开(公告)号：US06370056B1

公开(公告)日：2002-04-09

申请号：US09523492

申请日：2000-03-10

申请人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

发明人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line. A read MOSFET is connected between a drain input and the drain line associated with each row. The gate of the read MOSFET is connected to an input for the read enable signal.

摘要翻译： 一种铁电非易失性存储器，包括：多个存储单元，每个存储单元包含FeFET和MOSFET，每个所述FeFET具有源极，漏极，衬底和栅极，并且每个MOSFET具有一对源极/漏极 和一个门。 单元被布置成包括多行和多列的阵列。 栅极线和位线与每列相关联，并且字线，漏极线和衬底线与每一行相关联。 每个MOSFET的一个源极/漏极连接到其对应的栅极线; 另一个源极/漏极连接到电池中的FeFET的栅极。 MOSFET的栅极连接到提供写和擦除使能信号的相应字线。 FeFET的漏极连接到其对应的漏极线，并且FeFET的源极连接到其对应的位线。 每个FeFET的衬底连接到其相应的衬底线。 读取MOSFET连接在与每行相关联的漏极输入和漏极线之间。 读取MOSFET的栅极连接到读使能信号的输入端。

公开(公告)号：US06373743B1

公开(公告)日：2002-04-16

申请号：US09385308

申请日：1999-08-30

申请人： Zheng Chen ,  Myoungho Lim ,  Vikram Joshi ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

发明人： Zheng Chen ,  Myoungho Lim ,  Vikram Joshi ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source. Thus, the current in the selected column select line and row select line is a measure of the state of the selected cell. Each FET is fabricated using a self-aligned process so that no portion of a source/drain underlies the gate.

摘要翻译： 一种铁电非易失性存储器，包括：各自含有铁电FET的多个存储单元，每个所述铁电FET具有源极，漏极，基板和栅极。 FET被布置成包括多个行和多个列的阵列。 存在多个行选择线，每条线选择线与所述强电介质FET的行中的一条相关联，以及多个列选择线，每条列选择线与铁电FET中的一列相关联。 每个源直接电连接到其相关联的行选择线，并且每个漏极直接电连接到其相关联的列选择线。 每个FET的源极和衬底也直接电连接。 通过将其行选择线连接到地来读取存储单元，并且其列选择线为小电压。 所有的门和未选择的单元的行选择线是打开的或连接到高电阻源。 因此，所选列选择行和行选择行中的电流是所选单元格的状态的度量。 每个FET使用自对准工艺制造，使得源极/漏极的任何部分不在栅极之下。

公开(公告)号：US20050127874A1

公开(公告)日：2005-06-16

申请号：US10735010

申请日：2003-12-12

申请人： Myoungho Lim ,  Mark Flaherty ,  Woo-chul Yi ,  Keith Griffin

发明人： Myoungho Lim ,  Mark Flaherty ,  Woo-chul Yi ,  Keith Griffin

IPC分类号： H02J7/00

CPC分类号： H02J7/0019 ,  Y02T10/7055

摘要： Embodiments of the present invention are directed to a method and apparatus for multiple battery cell management. In one embodiment, a solid state relay is used instead of a mechanical relay in a BMS. The SSR is smaller and faster than a mechanical relay, enabling smaller BMSs that more efficiently and safely manage battery cell charge. In another embodiment, a plurality of battery cells are connected to two rails, using four SSRs to control access to the battery cells. In one embodiment, a plurality of battery cells are grouped together and controlled as one module of a multi-module BMS. In one embodiment, each module has 10 battery cells in series. In one embodiment, the BMS controls 4 modules. In one embodiment, each module is controlled by control signals passing through logical gates. In another embodiment, each module is controlled by control signals passing through a programmed circuit.

摘要翻译： 本发明的实施例涉及一种用于多个电池单元管理的方法和装置。 在一个实施例中，使用固态继电器代替BMS中的机械继电器。 SSR比机械继电器更小更快，可以使更小的BMS更有效和安全地管理电池电量。 在另一个实施例中，多个电池单元连接到两个导轨，使用四个SSR来控制对电池单元的访问。 在一个实施例中，多个电池单元被分组在一起并被控制为多模块BMS的一个模块。 在一个实施例中，每个模块具有串联的10个电池单元。 在一个实施例中，BMS控制4个模块。 在一个实施例中，每个模块由通过逻辑门的控制信号控制。 在另一个实施例中，每个模块由通过编程电路的控制信号控制。