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    Ferroelectric device with bismuth tantalate capping layer and method of making same
    1.
    发明授权
    Ferroelectric device with bismuth tantalate capping layer and method of making same 失效
    具有钽酸铋盖层的铁电元件及其制造方法

    公开(公告)号：US06437380B1

    公开(公告)日：2002-08-20

    申请号：US09819542

    申请日：2001-03-28

    申请人： Myoungho Lim ,  Vikram Joshi ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

    发明人： Myoungho Lim ,  Vikram Joshi ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

    IPC分类号： H01L2976

    CPC分类号： H01L29/516 ,  H01L28/56

    摘要： An integrated circuit device includes a thin film of bismuth-containing layered superlattice material having a thickness not exceeding 100 nm, a capping layer thin film of bismuth tantalate, and an electrode. The capping layer has a thickness in a range of from 3 nm to 30 nm and is deposited between the thin film of layered superlattice material and the electrode to increase dielectric breakdown voltage. Preferably the capping layer contains an excess amount of bismuth relative to the stoichiometrically balanced amount represented by the balanced stoichiometric formula BiTaO4. Preferably, the layered superlattice material is ferroelectric SBT or SBTN. Preferably, the integrated circuit device is a nonvolatile ferroelectric memory. Heating treatments for fabrication of the integrated circuit device containing the bismuth tantalate capping layerare conducted at temperatures not exceeding 700° C., preferably in a range of from 650° C. to 700° C.

    摘要翻译： 集成电路器件包括厚度不超过100nm的含铋层状超晶格材料薄膜，钽酸铋覆盖层薄膜和电极。 覆盖层的厚度在3nm至30nm的范围内，并且沉积在层状超晶格材料的薄膜和电极之间以增加介电击穿电压。 优选地，封盖层相对于由平衡化学计量式BiTaO 4表示的化学计量平衡量含有过量的铋。 优选地，层状超晶格材料是铁电SBT或SBTN。 优选地，集成电路器件是非易失性铁电存储器。 用于制造包含钽酸铋覆盖层的集成电路器件的加热处理在不超过700℃的温度下进行，优选在650℃至700℃的范围内。

    Barrier layers for protecting metal oxides from hydrogen degradation
    3.
    发明授权
    Barrier layers for protecting metal oxides from hydrogen degradation 有权
    用于保护金属氧化物免受氢降解的阻挡层

    公开(公告)号：US06781184B2

    公开(公告)日：2004-08-24

    申请号：US09998469

    申请日：2001-11-29

    申请人： Narayan Solayappan ,  Jolanta Celinska ,  Vikram Joshi ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Narayan Solayappan ,  Jolanta Celinska ,  Vikram Joshi ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： H01L27108

    CPC分类号： H01L28/57 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

    摘要翻译： 集成电路中的氢扩散阻挡层位于集成电路中以抑制氢扩散到诸如铁电层状超晶格材料的金属氧化物的薄膜。 氢扩散阻挡层包括以下化合物中的至少一种：钽酸锶，钽酸铋，氧化钽，氧化钛，氧化锆和氧化铝。 氢阻挡层是无定形的，并且在450℃或更低的温度下通过MOCVD工艺制成。 在与所述氢扩散阻挡层相邻的地方形成包括选自氮化硅和所述氢阻挡层材料之一的结晶形式的材料的补充氢阻挡层。

    Stacked memory cell having diffusion barriers
    4.
    发明授权
    Stacked memory cell having diffusion barriers 有权
    具有扩散阻挡层的堆积式存储单元

    公开(公告)号：US07187079B2

    公开(公告)日：2007-03-06

    申请号：US10666381

    申请日：2003-09-19

    申请人： Vikram Joshi ,  Narayan Solayappan ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Vikram Joshi ,  Narayan Solayappan ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11502 ,  C30B29/32 ,  C30B29/68 ,  H01L23/642 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

    摘要翻译： 非导电氢阻挡层沉积在基板上并完全覆盖集成电路存储单元的存储电容器和MOSFET开关上的表面积。 通过蚀刻去除与存储电容器的底部电极相邻的绝缘体层的一部分，以形成护城河区域。 沉积非导电氧阻隔层以覆盖护城河的侧壁和底部。 电容器下面的非导电氧阻挡层和导电扩散阻挡层一起在电容器和开关之间提供基本上连续的扩散阻挡层。 此外，非导电氢阻挡层，非导电氧阻挡层和导电扩散阻挡层基本上完全包围电容器，特别是电容器中的铁电薄膜。

    Low temperature oxidizing method of making a layered superlattice material
    7.
    发明授权
    Low temperature oxidizing method of making a layered superlattice material 有权
    制作层状超晶格材料的低温氧化法

    公开(公告)号：US06582972B1

    公开(公告)日：2003-06-24

    申请号：US09544697

    申请日：2000-04-07

    申请人： Vikram Joshi ,  Jolanta Celinska ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo ,  Koji Arita

    发明人： Vikram Joshi ,  Jolanta Celinska ,  Narayan Solayappan ,  Larry D. McMillan ,  Carlos A. Paz de Araujo ,  Koji Arita

    IPC分类号： H01G2100

    CPC分类号： H01L27/11502 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/31691

    摘要： A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100° C. to 300° C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500° C. to 700° C., preferably not exceeding 650° C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500° C. to 700° C. may precede annealing.

    摘要翻译： 将用于形成层状超晶格材料的前体薄膜施加到集成电路基板上，然后在100℃至300℃的低温下向前体薄膜施加强氧化剂，由此 形成金属氧化物薄膜。 强氧化剂可以是液体或气体。 液体强氧化剂的实例是过氧化氢。 气态强氧化剂的实例是臭氧。 金属氧化物薄膜通过在500℃至700℃，优选不超过650℃的范围内的升高温度退火30分钟至2小时的时间段而结晶。 退火在含氧气氛中进行，优选包括水蒸气。 紫外线（UV）辐射处理可能退火之前。 可以在退火之前从500℃到700℃的范围内的RTP。

    Stacked memory cell having diffusion barriers
    8.
    发明授权
    Stacked memory cell having diffusion barriers 有权
    具有扩散阻挡层的堆积式存储单元

    公开(公告)号：US06743643B2

    公开(公告)日：2004-06-01

    申请号：US10348706

    申请日：2003-01-22

    申请人： Vikram Joshi ,  Narayan Solayappan ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Vikram Joshi ,  Narayan Solayappan ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： H01G706

    CPC分类号： H01L27/11502 ,  C30B29/32 ,  C30B29/68 ,  H01L23/642 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

    摘要翻译： 非导电氢阻挡层沉积在基板上并完全覆盖集成电路存储单元的存储电容器和MOSFET开关上的表面积。 通过蚀刻去除与存储电容器的底部电极相邻的绝缘体层的一部分，以形成护城河区域。 沉积非导电氧阻隔层以覆盖护城河的侧壁和底部。 电容器下面的非导电氧阻挡层和导电扩散阻挡层一起在电容器和开关之间提供基本上连续的扩散阻挡层。 此外，非导电氢阻挡层，非导电氧阻挡层和导电扩散阻挡层基本上完全包围电容器，特别是电容器中的铁电薄膜。

    Ferroelectric and high dielectric constant transistors
    10.
    发明授权
    Ferroelectric and high dielectric constant transistors 失效
    铁电和高介电常数晶体管

    公开(公告)号：US06559469B1

    公开(公告)日：2003-05-06

    申请号：US09686552

    申请日：2000-10-11

    申请人： Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Vikram Joshi ,  Narayan Solayappan ,  Joseph D. Cuchiaro

    发明人： Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Vikram Joshi ,  Narayan Solayappan ,  Joseph D. Cuchiaro

    IPC分类号： H01L2972

    CPC分类号： H01L27/11502 ,  C23C16/448 ,  C23C16/45561 ,  C23C18/1216 ,  C23C18/14 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  G11C11/22 ,  G11C11/223 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55 ,  H01L28/60

    摘要： An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.

    摘要翻译： 集成电路包括具有公式A1w1 + a1A2w2 + a2的分层超晶格材料。 。 。 Ajwj + ajS1x1 + s1S2x2 + s2。 。 。 Skxk + skB1y1 + b1B2y2 + b2。 。 。 Blyl + blQz-q，其中A1，A2。 。 。 Aj代表钙钛矿结构中的A位元素，S1，S2。 。 。 Sk代表超晶格发生器元件B1，B2。 。 。 B1表示钙钛矿结构中的B位元素，Q表示阴离子，上标表示各元素的化合价，下标表示单元中元素的原子数，并且至少w1和y1为 非零。 这些材料中的一些是非常低的疲劳铁电体，并且被应用在非易失性存储器中的铁电FET中。 其他的是高介电常数材料，其在长期使用中不会劣化或分解，并且作为在绝缘体中的栅绝缘体。