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    SHARED NONVOLATILE MEMORY ARCHITECTURE
    1.
    发明申请
    SHARED NONVOLATILE MEMORY ARCHITECTURE 有权
    共享非易失性存储器架构

    公开(公告)号：US20070233938A1

    公开(公告)日：2007-10-04

    申请号：US11690629

    申请日：2007-03-23

    申请人： Myung Cho ,  Dongyun Lee ,  Alan Ruberg

    发明人： Myung Cho ,  Dongyun Lee ,  Alan Ruberg

    IPC分类号： G06F12/00

    CPC分类号： G06F15/177 ,  G06F9/4405

    摘要： A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

    摘要翻译： 一种利用共享非易失性存储器来初始化设备中的多个处理组件的方法和系统。 用于处理设备内的组件的启动逻辑和配置数据存储在单个非易失性存储器中。 在接收到用于初始化设备的命令时，共享存储器系统将启动逻辑和配置数据从非易失性存储器复制到易失性主存储器。 然后，每个处理组件访问主存储器以找到其启动逻辑和配置数据并开始执行。 共享存储器系统减少用于初始化多个处理组件的非易失性存储器组件的数量。

    INTER-PORT COMMUNICATION IN A MULTI-PORT MEMORY DEVICE
    2.
    发明申请
    INTER-PORT COMMUNICATION IN A MULTI-PORT MEMORY DEVICE 有权
    多端口存储器中的端口间通信

    公开(公告)号：US20070234021A1

    公开(公告)日：2007-10-04

    申请号：US11694819

    申请日：2007-03-30

    申请人： Alan Ruberg ,  Dae Kim ,  Daeyun Shim ,  Dongyun Lee ,  Myung Cho ,  Sungjoon Kim

    发明人： Alan Ruberg ,  Dae Kim ,  Daeyun Shim ,  Dongyun Lee ,  Myung Cho ,  Sungjoon Kim

    IPC分类号： G06F7/38

    CPC分类号： G11C8/16 ,  G06F13/4054 ,  G06F13/4243 ,  G11C7/1075 ,  G11C2207/108

    摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

    摘要翻译： 一种利用多端口存储器件进行端口间通信的方法和系统。 存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。 当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时，第一组件将消息写入与第二端口相关联的消息缓冲器。 第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。 在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。 然后第二个组件从消息缓冲区读取消息。

    Shared nonvolatile memory architecture
    3.
    发明授权
    Shared nonvolatile memory architecture 有权
    共享非易失性存储器架构

    公开(公告)号：US07831778B2

    公开(公告)日：2010-11-09

    申请号：US11690629

    申请日：2007-03-23

    申请人： Myung Rai Cho ,  Dongyun Lee ,  Alan Ruberg

    发明人： Myung Rai Cho ,  Dongyun Lee ,  Alan Ruberg

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/00 ,  G06F9/24 ,  G06F15/177

    CPC分类号： G06F15/177 ,  G06F9/4405

    摘要： A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

    摘要翻译： 一种利用共享非易失性存储器来初始化设备中的多个处理组件的方法和系统。 用于处理设备内的组件的启动逻辑和配置数据存储在单个非易失性存储器中。 在接收到用于初始化设备的命令时，共享存储器系统将启动逻辑和配置数据从非易失性存储器复制到易失性主存储器。 然后，每个处理组件访问主存储器以找到其启动逻辑和配置数据并开始执行。 共享存储器系统减少用于初始化多个处理组件的非易失性存储器组件的数量。

    MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS
    6.
    发明申请
    MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 有权
    具有可变端口速度的多端口存储器件

    公开(公告)号：US20070245094A1

    公开(公告)日：2007-10-18

    申请号：US11694813

    申请日：2007-03-30

    申请人： Dongyun Lee ,  Myung Cho ,  Sungjoon Kim

    发明人： Dongyun Lee ,  Myung Cho ,  Sungjoon Kim

    IPC分类号： G06F13/00

    CPC分类号： G11C8/16 ,  G06F13/4054 ,  G06F13/4243 ,  G11C7/1075 ,  G11C2207/108

    摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.

    摘要翻译： 具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。 多端口存储器件包含可通过两个或更多个端口访问的存储器组。 每个端口都应用两个时钟信号：系统时钟和端口时钟。 系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。 端口时钟应用于与每个端口相关联的时钟分频器电路。 端口时钟被分为所需频率或保持在其原始频率。 这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

    VIDEO MANAGEMENT AND CONTROL IN HOME MULTIMEDIA NETWORK
    8.
    发明申请
    VIDEO MANAGEMENT AND CONTROL IN HOME MULTIMEDIA NETWORK 有权
    家庭多媒体网络中的视频管理和控制

    公开(公告)号：US20130191872A1

    公开(公告)日：2013-07-25

    申请号：US13521762

    申请日：2011-01-12

    申请人： Dongyun Lee ,  Edward Pak ,  John Hahn ,  Mayank Gupta ,  Byoung Woon Kim ,  Paul Heninwolf ,  Sangwan Kim ,  Sukjae Cho

    发明人： Dongyun Lee ,  Edward Pak ,  John Hahn ,  Mayank Gupta ,  Byoung Woon Kim ,  Paul Heninwolf ,  Sangwan Kim ,  Sukjae Cho

    IPC分类号： H04N21/63

    CPC分类号： H04N21/43615 ,  G06F13/4286 ,  G09G2370/047 ,  G09G2370/12 ,  H04L12/2838 ,  H04L2012/2849 ,  H04N21/43632 ,  H04N21/43635 ,  H04N21/63

    摘要： A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link.

    摘要翻译： 系统可以包括将发送设备连接到接收设备的视频链路和混合链路，以及发送设备和接收设备之间的至少一个中间跳。 中间跳可以被配置为使用一个或多个数据中继模式通过混合链路将视频内容从视频源中继到视频接收器。 混合链路可以被配置为执行混合链路控制信令（HLCS）以管理混合链路的物理层。 视频源和视频接收器之间的视频链路可以被配置为通过一个或多个视频通道将视频源的视频流传输到视频接收器。 可以为视频链路和混合链路实现视频链路训练。

    Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer
    9.
    发明授权
    Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer 有权
    具有可控加权的并行高通和低通滤波器的均衡器和包括这种均衡器的接收器

    公开(公告)号：US08275026B2

    公开(公告)日：2012-09-25

    申请号：US11796175

    申请日：2007-04-27

    申请人： Dongyun Lee

    发明人： Dongyun Lee

    IPC分类号： H03H7/40

    CPC分类号： H04L25/03159 ,  H04L63/04 ,  H04L63/166 ,  H04L2025/03356 ,  H04L2025/03522

    摘要： An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (β), and a second branch including a high pass filter (HPF) and having another variable gain (α). The equalizer can be implemented using CMOS technology so that the gain parameters β and α are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. In some embodiments, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0·(β+α·(1+s·C0·Z0)), where β is a gain parameter determined by the tail current of one differential pair and α is a gain parameter determined by the tail current of the other differential pair.

    摘要翻译： 一种可调均衡器，其包括包括低通滤波器（LPF）并具有可变增益的第一分支（＆amp; bgr），以及包括高通滤波器（HPF）并具有另一可变增益（α）的第二分支。 均衡器可以使用CMOS技术实现，使得增益参数＆bgr; α是独立可调的，并且均衡器能够均衡指示具有至少1Gb / s的最大数据速率的数据的输入。 在一些实施例中，均衡器包括两个MOS晶体管的差分对，并且可控电流源确定每个差分对的尾电流。 当均衡器包括纯电阻阻抗Z0和Z1时，均衡器的传递函数为Z1 / Z0·（＆bgr; +α·（1 + s·C0·Z0）），其中＆bgr; 是由一个差分对的尾部电流确定的增益参数，α是由另一个差分对的尾部电流确定的增益参数。

    Progressive power control of a multi-port memory device
    10.
    发明授权
    Progressive power control of a multi-port memory device 有权
    多端口存储设备的逐行功率控制

    公开(公告)号：US07908501B2

    公开(公告)日：2011-03-15

    申请号：US11690642

    申请日：2007-03-23

    申请人： Sungjoon Kim ,  Dongyun Lee ,  Edward Kim

    发明人： Sungjoon Kim ,  Dongyun Lee ,  Edward Kim

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1075 ,  G11C7/22 ,  Y02D10/14 ,  Y02D50/20

    摘要： A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.

    摘要翻译： 提供了一种逐渐降低串行存储设备的功耗的方法和系统，称为功率控制系统。 电源控制系统监视多端口串行存储器的端口，以便可以在每个端口的基础上启用或禁用它们。 当在端口上没有发送或接收数据时，采取一系列步骤逐步取消对端口的部分断电并使端口进入低功率状态。 通过禁用某些端口并将端口置于低功耗状态，整个串行端口存储器的功耗显着降低。