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    Value transfer between program variables using dynamic memory resource mapping
    1.
    发明授权
    Value transfer between program variables using dynamic memory resource mapping 有权

    公开(公告)号：US09733911B2

    公开(公告)日：2017-08-15

    申请号：US14938649

    申请日：2015-11-11

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Hojin Kee ,  Tai A. Ly ,  David C. Uliana ,  Adam T. Arnesen ,  Newton G. Petersen

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F8/34

    Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

    Incremental loop modification for LDPC encoding
    2.
    发明授权
    Incremental loop modification for LDPC encoding 有权

    公开(公告)号：US10367525B2

    公开(公告)日：2019-07-30

    申请号：US14725914

    申请日：2015-05-29

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： David C. Uliana ,  Newton G. Petersen ,  Tai A. Ly ,  Hojin Kee ,  Adam T. Arnesen ,  Dustyn K. Blasig ,  Gandiinaa Gumenjav

    IPC: H03M13/03 ,  H03M13/11 ,  H03M13/00 ,  H04L1/00

    Abstract: Techniques are disclosed relating to encoding communications. In some embodiments, for different rows of an encoding matrix, the following operations are performed: generate a set of operations for entries in the row, where the set of operations includes respective operations to be performed on the entries for multiplication of the matrix by a vector, propagate values of entries in the encoding matrix into the set of operations, and simplify ones of the set of operations based on the propagated values to generate an output set of operations. In some embodiments, the output sets of operations are usable to encode input data for communication over a medium. In some embodiments, the disclosed techniques facilitate loop unrolling within compiler memory constraints. In some embodiments, an apparatus (e.g., a mobile device) is configured with the output sets of operations.

    Value Transfer between Program Variables using Dynamic Memory Resource Mapping
    3.
    发明申请
    Value Transfer between Program Variables using Dynamic Memory Resource Mapping 有权

    公开(公告)号：US20170131984A1

    公开(公告)日：2017-05-11

    申请号：US14938649

    申请日：2015-11-11

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Hojin Kee ,  Tai A. Ly ,  David C. Uliana ,  Adam T. Arnesen ,  Newton G. Petersen

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F8/34

    Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

    Configuring Circuitry with Memory Access Constraints for a Program
    4.
    发明申请
    Configuring Circuitry with Memory Access Constraints for a Program 有权
    配置电路与程序的内存访问约束

    公开(公告)号：US20160070499A1

    公开(公告)日：2016-03-10

    申请号：US14523039

    申请日：2014-10-24

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Tai A. Ly ,  Swapnil D. Mhaske ,  Hojin Kee ,  Adam T. Arnesen ,  David C. Uliana ,  Newton G. Petersen

    IPC: G06F3/06 ,  H03M13/11

    CPC classification number: G06F3/0616 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F11/1076 ,  G06F13/1615 ,  G06F13/1626 ,  G11C7/1039 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6563 ,  H03M13/6566 ,  H03M13/6569 ,  Y02D10/14

    Abstract: Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

    Abstract translation: 公开了关于配置互锁存储器系统的技术。 在一个实施例中，一种方法包括确定程序的存储器访问请求的序列，以及基于所述存储器访问序列产生指定存储器访问约束的信息，其中所述信息可用于避免所述存储器访问序列的存储器访问危险。 在该实施例中，该方法还包括使用该信息配置第一电路，其中第一电路被包括在存储器中或耦合到存储器。 在该实施例中，在配置之后，第一电路可操作以在不接收指示存储器访问危险的其它信息的同时避免存储器访问危险的同时对与存储器访问序列相对应的存储器执行存储器访问请求。

    Self-addressing memory
    5.
    发明授权
    Self-addressing memory 有权

    公开(公告)号：US10331361B2

    公开(公告)日：2019-06-25

    申请号：US15397107

    申请日：2017-01-03

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Tai A. Ly ,  Swapnil D. Mhaske ,  Hojin Kee ,  Adam T. Arnesen ,  David C. Uliana ,  Newton G. Petersen

    IPC: G06F3/06 ,  H03M13/11 ,  G06F11/10 ,  G06F13/16 ,  G11C7/10 ,  H03M13/00

    Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

    Single-IC LDPC Encoding and Decoding Implementations
    8.
    发明申请
    Single-IC LDPC Encoding and Decoding Implementations 有权
    单IC LDPC编码和解码实现

    公开(公告)号：US20160352355A1

    公开(公告)日：2016-12-01

    申请号：US14725812

    申请日：2015-05-29

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： David C. Uliana ,  James W. McCoy ,  Newton G. Petersen ,  Tai A. Ly ,  Hojin Kee ,  Adam T. Arnesen

    IPC: H03M13/11 ,  G06F11/10

    CPC classification number: G06F11/1008 ,  H03M13/1102 ,  H03M13/116 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6561

    Abstract: Techniques are disclosed relating to implementation of LDPC encoding circuitry on a single integrated circuit (IC). In some embodiments, circuitry on a single IC includes message circuitry configured to receive or generate a message to be encoded, encode circuitry configured to perform low density parity check (LDPC) encoding on the message, noise circuitry configured to apply noise to the encoded message, and decode circuitry configured to perform LDPC decoding of the message. In some embodiments, the disclosed techniques may reduce production costs (e.g., by reducing overall chip area), facilitate LDPC testing, and/or provide multiple different functions relating to message transmission on a single chip.

    Abstract translation: 公开了关于单个集成电路（IC）上的LDPC编码电路的实现的技术。 在一些实施例中，单个IC上的电路包括被配置为接收或生成要编码的消息的消息电路，被配置为对该消息执行低密度奇偶校验（LDPC）编码的编码电路，被配置为将噪声应用于编码消息的噪声电路 以及被配置为执行消息的LDPC解码的解码电路。 在一些实施例中，所公开的技术可以降低生产成本（例如，通过减少总体芯片面积），促进LDPC测试，和/或提供与单个芯片上的消息传输相关的多个不同功能。

    Reordering a Sequence of Memory Accesses to Improve Pipelined Performance
    9.
    发明申请
    Reordering a Sequence of Memory Accesses to Improve Pipelined Performance 审中-公开
    重新排序内存访问序列，以改善流水线性能

    公开(公告)号：US20160070662A1

    公开(公告)日：2016-03-10

    申请号：US14523232

    申请日：2014-10-24

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Tai A. Ly ,  Swapnil D. Mhaske ,  Hojin Kee ,  Adam T. Arnesen ,  David C. Uliana ,  Newton G. Petersen

    IPC: G06F13/16 ,  G11C7/10

    CPC classification number: G06F3/0616 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F11/1076 ,  G06F13/1615 ,  G06F13/1626 ,  G11C7/1039 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6563 ,  H03M13/6566 ,  H03M13/6569 ,  Y02D10/14

    Abstract: Techniques are disclosed relating to reordering sequences of memory accesses. In one embodiment, a method includes storing a specified sequence of memory accesses that corresponds to a function to be performed. In this embodiment, the specified sequence of memory accesses has first memory access constraints. In this embodiment, the method further includes reordering the specified sequence of memory accesses to create a reordered sequence of memory accesses that has second, different memory access constraints. In this embodiment, the reordered sequence of memory accesses is usable to access a memory to perform the function. In some embodiments, performance estimates are determined for a plurality of reordered sequences of memory accesses, and one of the reordered sequences is selected based on the performance estimates. In some embodiments, the reordered sequence is used to compile a program usable to perform the function.

    Abstract translation: 公开了关于重新排序存储器访问序列的技术。 在一个实施例中，一种方法包括存储与要执行的功能相对应的指定的存储器访问序列。 在该实施例中，指定的存储器访问序列具有第一存储器访问限制。 在该实施例中，该方法还包括重新排序指定的存储器访问序列以创建具有第二不同存储器访问限制的重新排序的存储器访问序列。 在该实施例中，存储器访问的重排序列可用于访问存储器以执行该功能。 在一些实施例中，为多个重新排序的存储器访问序列确定性能估计，并且基于性能估计来选择重新排序的序列中的一个。 在一些实施例中，重新排序的序列用于编译可用于执行该功能的程序。

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