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    Self-addressing memory
    1.
    发明授权
    Self-addressing memory 有权

    公开(公告)号：US10331361B2

    公开(公告)日：2019-06-25

    申请号：US15397107

    申请日：2017-01-03

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Tai A. Ly ,  Swapnil D. Mhaske ,  Hojin Kee ,  Adam T. Arnesen ,  David C. Uliana ,  Newton G. Petersen

    IPC: G06F3/06 ,  H03M13/11 ,  G06F11/10 ,  G06F13/16 ,  G11C7/10 ,  H03M13/00

    Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

    Single-IC LDPC Encoding and Decoding Implementations
    4.
    发明申请
    Single-IC LDPC Encoding and Decoding Implementations 有权
    单IC LDPC编码和解码实现

    公开(公告)号：US20160352355A1

    公开(公告)日：2016-12-01

    申请号：US14725812

    申请日：2015-05-29

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： David C. Uliana ,  James W. McCoy ,  Newton G. Petersen ,  Tai A. Ly ,  Hojin Kee ,  Adam T. Arnesen

    IPC: H03M13/11 ,  G06F11/10

    CPC classification number: G06F11/1008 ,  H03M13/1102 ,  H03M13/116 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6561

    Abstract: Techniques are disclosed relating to implementation of LDPC encoding circuitry on a single integrated circuit (IC). In some embodiments, circuitry on a single IC includes message circuitry configured to receive or generate a message to be encoded, encode circuitry configured to perform low density parity check (LDPC) encoding on the message, noise circuitry configured to apply noise to the encoded message, and decode circuitry configured to perform LDPC decoding of the message. In some embodiments, the disclosed techniques may reduce production costs (e.g., by reducing overall chip area), facilitate LDPC testing, and/or provide multiple different functions relating to message transmission on a single chip.

    Abstract translation: 公开了关于单个集成电路（IC）上的LDPC编码电路的实现的技术。 在一些实施例中，单个IC上的电路包括被配置为接收或生成要编码的消息的消息电路，被配置为对该消息执行低密度奇偶校验（LDPC）编码的编码电路，被配置为将噪声应用于编码消息的噪声电路 以及被配置为执行消息的LDPC解码的解码电路。 在一些实施例中，所公开的技术可以降低生产成本（例如，通过减少总体芯片面积），促进LDPC测试，和/或提供与单个芯片上的消息传输相关的多个不同功能。

    Correlation Analysis of Program Structures
    5.
    发明申请
    Correlation Analysis of Program Structures 有权
    程序结构的相关分析

    公开(公告)号：US20160103664A1

    公开(公告)日：2016-04-14

    申请号：US14510441

    申请日：2014-10-09

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Hojin Kee ,  Haoran Yi ,  Tai A. Ly ,  Newton G. Petersen ,  James M. Lewis ,  Dustyn K. Blasig ,  Adam T. Arnesen ,  Taylor L. Riche

    IPC: G06F9/45 ,  G06F9/44

    CPC classification number: G06F8/443 ,  G06F8/20 ,  G06F8/34

    Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

    Abstract translation: 执行相关分析的系统和方法。 存储包括多个程序结构和一个或多个数据对象的程序。 每个数据对象由至少两个程序结构共享。 对于每个程序结构，分析由应用于程序结构的相应的一个或多个优化变换中的每一个产生的由程序结构共享的每个数据对象的分解效果。 基于分析确定一组或多组相关结构。 每个组包括共享至少一个数据对象的两个或更多个程序结构，以及与两个或多个程序结构和共享数据对象兼容的至少一个优化变换。 对于至少一个组，所述至少一个优化变换可用于变换所述两个或多个程序结构以满足指定的优化目标。

    Reordering a Sequence of Memory Accesses to Improve Pipelined Performance
    6.
    发明申请
    Reordering a Sequence of Memory Accesses to Improve Pipelined Performance 审中-公开
    重新排序内存访问序列，以改善流水线性能

    公开(公告)号：US20160070662A1

    公开(公告)日：2016-03-10

    申请号：US14523232

    申请日：2014-10-24

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Tai A. Ly ,  Swapnil D. Mhaske ,  Hojin Kee ,  Adam T. Arnesen ,  David C. Uliana ,  Newton G. Petersen

    IPC: G06F13/16 ,  G11C7/10

    CPC classification number: G06F3/0616 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F11/1076 ,  G06F13/1615 ,  G06F13/1626 ,  G11C7/1039 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6563 ,  H03M13/6566 ,  H03M13/6569 ,  Y02D10/14

    Abstract: Techniques are disclosed relating to reordering sequences of memory accesses. In one embodiment, a method includes storing a specified sequence of memory accesses that corresponds to a function to be performed. In this embodiment, the specified sequence of memory accesses has first memory access constraints. In this embodiment, the method further includes reordering the specified sequence of memory accesses to create a reordered sequence of memory accesses that has second, different memory access constraints. In this embodiment, the reordered sequence of memory accesses is usable to access a memory to perform the function. In some embodiments, performance estimates are determined for a plurality of reordered sequences of memory accesses, and one of the reordered sequences is selected based on the performance estimates. In some embodiments, the reordered sequence is used to compile a program usable to perform the function.

    Abstract translation: 公开了关于重新排序存储器访问序列的技术。 在一个实施例中，一种方法包括存储与要执行的功能相对应的指定的存储器访问序列。 在该实施例中，指定的存储器访问序列具有第一存储器访问限制。 在该实施例中，该方法还包括重新排序指定的存储器访问序列以创建具有第二不同存储器访问限制的重新排序的存储器访问序列。 在该实施例中，存储器访问的重排序列可用于访问存储器以执行该功能。 在一些实施例中，为多个重新排序的存储器访问序列确定性能估计，并且基于性能估计来选择重新排序的序列中的一个。 在一些实施例中，重新排序的序列用于编译可用于执行该功能的程序。

    Value transfer between program variables using dynamic memory resource mapping
    8.
    发明授权
    Value transfer between program variables using dynamic memory resource mapping 有权

    公开(公告)号：US09733911B2

    公开(公告)日：2017-08-15

    申请号：US14938649

    申请日：2015-11-11

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Hojin Kee ,  Tai A. Ly ,  David C. Uliana ,  Adam T. Arnesen ,  Newton G. Petersen

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F8/34

    Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

    Staged program compilation with automated timing closure
    9.
    发明授权
    Staged program compilation with automated timing closure 有权
    分阶段的程序编译与自动时序关闭

    公开(公告)号：US09558099B2

    公开(公告)日：2017-01-31

    申请号：US14807610

    申请日：2015-07-23

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Jeffrey N. Correll ,  Dustyn K. Blasig ,  Newton G. Petersen

    IPC: G06F17/50 ,  G06F11/36 ,  G06F9/45 ,  G06F9/44

    CPC classification number: G06F11/362 ,  G06F8/30 ,  G06F8/34 ,  G06F8/41

    Abstract: When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass.

    Abstract translation: 当将高级图形代码（例如LabVIEW™代码）编译成不同的表示（例如不同的软件代码或硬件FPGA）时，可能会从编译过程中收集/捕获与设计特征有关的信息，并自动提供给所有 编译过程的早期阶段获得更优化的结果。 没有对这些信息的自动反馈，用户必须手动识别，生成和提供反馈信息，或放弃过程，必须假设该工具已经产生了尽可能最好的结果。 为了纠正时序，可能会解析失败的约束路径，并将其与先前编译期间获得的延迟进行比较，而不能产生预期结果的先前调整可能会被撤销。 然后可以识别和调整不是由未消除路径引起的最长延迟，并且可以重复该过程，直到预测所有路径通过。

    Specifying and implementing relative hardware clocking in a high level programming language
    10.
    发明授权
    Specifying and implementing relative hardware clocking in a high level programming language 有权
    以高级编程语言指定和实现相对硬件时钟

    公开(公告)号：US09411920B2

    公开(公告)日：2016-08-09

    申请号：US14107476

    申请日：2013-12-16

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： Dustyn K. Blasig ,  Newton G. Petersen ,  Matthew E. Novacek ,  Julian G. Valdez

    IPC: G06F17/50

    CPC classification number: G06F17/5059 ,  G06F8/34 ,  G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

    Abstract: System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion.

    Abstract translation: 用于以高级编程语言指定和实现相对硬件时钟的系统和方法。 可以接收指定程序的用户输入。 该程序被指定用于部署到可编程硬件元件（PHE），并且包括配置为在执行期间彼此通信的第一和第二代码部分。 用户输入还可以指定第一和第二代码部分的相应执行率的有理比率。 自动产生实现指定程序的硬件配置程序（HCP），包括基于有理比率自动确定第一和第二代码部分中的至少一个的相应时钟速率。 HCP可以部署到PHE，包括根据有理比率实现第一和第二时钟，用于控制第一和第二代码部分的执行，以及自动确定的至少一个代码部分的相应时钟速率。

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