公开(公告)号：US20020085157A1

公开(公告)日：2002-07-04

申请号：US10028778

申请日：2001-12-28

Applicant: NEC CORPORATION

Inventor： Hiroaki Tanaka ,  Akira Fujita ,  Shigeru Kimura ,  Akitoshi Maeda ,  Takasuke Hayase

IPC: G02F001/1343

CPC classification number: H01L29/4908 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L29/458

Abstract: An active matrix addressing LCD device having an active matrix substrate on which conductive lines are formed is provided, which suppress the Al hillock without complicating the structure of the lines and which decreases the electrical connection resistance increase at the terminals of the lines, thereby improving the connection reliability. The device comprises an active matrix substrate having a transparent, dielectric plate, thin-film transistors (TFTs) arranged on the plate, and pixel electrodes arranged on the plate. Gate electrodes of the TFTs and scan lines have a first multilevel conductive structure. Common electrodes and common lines may have the first multilevel conductive structure. Source and drain electrodes of the TFTs and signal lines may have a second multilevel conductive structure. Each of the first and second multilevel conductive structures includes a three-level TiN/Ti/Al or TiN/Al/Ti structure or a four-level TiN/Ti/Al/Ti structure. Each of the TiN film of the first and second structures has a nitrogen concentration of 25 atomic % or higher. The Al film may be replaced with an Al alloy.

Abstract translation: 提供了一种有源矩阵寻址LCD装置，其具有形成有导电线的有源矩阵基板，其抑制Al小丘而不使线路的结构复杂化，并且降低了线路端子处的电连接电阻增加，从而改善了 连接可靠性。 该器件包括具有透明电介质板，布置在板上的薄膜晶体管（TFT）和布置在板上的像素电极的有源矩阵基板。 TFT和扫描线的栅极具有第一多层导电结构。 公共电极和公共线可以具有第一多层导电结构。 TFT和信号线的源极和漏极可以具有第二多层导电结构。 第一和第二多层导电结构中的每一个包括三级TiN / Ti / Al或TiN / Al / Ti结构或四级TiN / Ti / Al / Ti结构。 第一和第二结构的TiN膜的氮浓度为25原子％以上。 Al膜可以用Al合金代替。

公开(公告)号：US20020009890A1

公开(公告)日：2002-01-24

申请号：US09903244

申请日：2001-07-11

Applicant: NEC Corporation

Inventor： Takasuke Hayase ,  Hiroaki Tanaka ,  Shusaku Kido ,  Toshihiko Harano

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L29/66765 ,  G02F1/136204 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/78633

Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.

Abstract translation: 将作为诸如TFT的栅电极的下层的第一导电膜图案与作为诸如TFT的源/漏电极的上层的第二导电膜图案连接的光刻工艺被减少 利用层叠膜和形成在其上的具有不同膜厚度的抗蚀剂图案。 构成源极/漏极的叠层膜通过在其上形成有第一导电膜图案的绝缘基板上沉积膜形成，并且在层压膜的顶层上形成抗蚀剂图案，然后利用膜厚度差 层叠膜的抗蚀剂图案和膜组成，有源矩阵基板的静电放电保护电路的栅极电极和源极/漏极之间的短路布线可以通过较少的光刻工艺形成， 常规有源矩阵基板的制造。

公开(公告)号：US20010010370A1

公开(公告)日：2001-08-02

申请号：US09745657

申请日：2000-12-20

Applicant: NEC Corporation

Inventor： Shigeru Kimura ,  Takahiko Watanabe ,  Tae Yoshikawa ,  Hiroyuki Uchida ,  Shusaku Kido ,  Shinichi Nakata ,  Tsutomu Hamada ,  Hisanobu Shimodouzono ,  Satoshi Doi ,  Toshihiko Harano ,  Akitoshi Maeda ,  Satoshi Ihida ,  Hiroaki Tanaka ,  Takasuke Hayase ,  Shouichi Kuroha ,  Hirofumi Ihara ,  Kazushige Takechi

IPC: H01L021/00 ,  H01L031/036

CPC classification number: G02F1/134363

Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and nnull amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the nnull amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.

Abstract translation: 使用四个光刻制造步骤以高产率制造具有优异性能的有源矩阵基板。 在步骤1中，在玻璃板上形成扫描线和从扫描线延伸的栅电极。 在步骤2中，层叠由非晶硅层和n +非晶硅层构成的栅极绝缘层和半导体层，为TFT部分提供半导体层。 在步骤3中，层叠透明导电层和金属层，形成信号线，从信号线延伸的漏极，从像素电极延伸的像素电极和源电极，并且n +非晶硅层 通过蚀刻去除通道间隙。 在步骤4中，形成保护绝缘层，通过蚀刻除去保护绝缘层和像素电极上方的金属层。