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    Load/store operations in texture hardware
    2.
    发明授权
    Load/store operations in texture hardware 有权
    在纹理硬件中加载/存储操作

    公开(公告)号：US09595075B2

    公开(公告)日：2017-03-14

    申请号：US14038599

    申请日：2013-09-26

    Applicant: NVIDIA CORPORATION

    Inventor： Steven J. Heinrich ,  Eric T. Anderson ,  Jeffrey A. Bolz ,  Jonathan Dunaisky ,  Ramesh Jandhyala ,  Joel McCormack ,  Alexander L. Minkin ,  Bryon S. Nordquist ,  Poornachandra Rao

    IPC: G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G09G5/36

    CPC classification number: G06T1/60 ,  G06F2212/302 ,  G06T1/20 ,  G06T15/04 ,  G09G5/363

    Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

    Abstract translation: 公开了用于在具有被配置为处理纹理存储器访问操作的第一部分的纹理处理流水线中执行存储器访问操作的方法和被配置为处理非纹理存储器访问操作的第二部分。 纹理单元接收存储器访问请求。 纹理单元确定存储器访问请求是否包括纹理存储器访问操作。 如果存储器访问请求包括纹理存储器访问操作，则纹理单元至少通过纹理处理流水线的第一部分来处理存储器访问请求，否则，纹理单元至少经由第二部分处理存储器访问请求 纹理处理流水线。 所公开方法的一个优点是可以将相同的处理和高速缓冲存储器用于纹理操作和对各种其他地址空间的加载/存储操作，导致减少的表面积和功率消耗。

    Technique for accessing content-addressable memory
    3.
    发明授权
    Technique for accessing content-addressable memory 有权
    访问内容可寻址内存的技术

    公开(公告)号：US09348762B2

    公开(公告)日：2016-05-24

    申请号：US13720755

    申请日：2012-12-19

    Applicant: NVIDIA CORPORATION

    Inventor： Brian Fahs ,  Eric T. Anderson ,  Nick Barrow-Williams ,  Shirish Gadre ,  Joel James McCormack ,  Bryon S. Nordquist ,  Nirmal Raj Saxena ,  Lacky V. Shah

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/1018

    Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

    Abstract translation: 配置为管理高速缓存单元的标签单元包括实现集合散列函数的聚结器。 集合散列函数将虚拟地址映射到特定的内容可寻址存储器单元（CAM）。 聚合器通过将虚拟地址分割成上部，中部和下部来实现集合散列函数。 上部分进一步分为偶数位和奇数索引位。 使用XOR树将偶数索引位减少到单个位，并且奇数索引以类似的方式减少。 这些单个位与虚拟地址的中间部分组合以提供识别特定CAM的CAM号码。 查询所识别的CAM以确定虚拟地址的标签部分的存在，指示高速缓存命中或高速缓存未命中。

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