公开(公告)号：US10032246B2

公开(公告)日：2018-07-24

申请号：US14049557

申请日：2013-10-09

Applicant: NVIDIA CORPORATION

Inventor： Eric T. Anderson ,  Poornachandra Rao

IPC: G06T11/40 ,  G06T1/60

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

公开(公告)号：US09720858B2

公开(公告)日：2017-08-01

申请号：US13720745

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Eric T. Anderson ,  Nick Barrow-Williams ,  Shirish Gadre ,  Joel James McCormack ,  Bryon S. Nordquist ,  Nirmal Raj Saxena ,  Lacky V. Shah

IPC: G06F13/28 ,  G06F13/14 ,  G06T1/20 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06F13/14 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/36

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

公开(公告)号：US09697006B2

公开(公告)日：2017-07-04

申请号：US13720746

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Eric T. Anderson ,  Nick Barrow-Williams ,  Shirish Gadre ,  Joel James McCormack ,  Bryon S. Nordquist ,  Nirmal Raj Saxena ,  Lacky V. Shah

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/0844 ,  G06F12/0815 ,  G06F12/02

CPC classification number: G06F9/3887 ,  G06F9/3851 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0844 ,  G06F2209/5018 ,  G06F2212/604

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

公开(公告)号：US09595075B2

公开(公告)日：2017-03-14

申请号：US14038599

申请日：2013-09-26

Applicant: NVIDIA CORPORATION

Inventor： Steven J. Heinrich ,  Eric T. Anderson ,  Jeffrey A. Bolz ,  Jonathan Dunaisky ,  Ramesh Jandhyala ,  Joel McCormack ,  Alexander L. Minkin ,  Bryon S. Nordquist ,  Poornachandra Rao

IPC: G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G09G5/36

CPC classification number: G06T1/60 ,  G06F2212/302 ,  G06T1/20 ,  G06T15/04 ,  G09G5/363

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract translation: 公开了用于在具有被配置为处理纹理存储器访问操作的第一部分的纹理处理流水线中执行存储器访问操作的方法和被配置为处理非纹理存储器访问操作的第二部分。 纹理单元接收存储器访问请求。 纹理单元确定存储器访问请求是否包括纹理存储器访问操作。 如果存储器访问请求包括纹理存储器访问操作，则纹理单元至少通过纹理处理流水线的第一部分来处理存储器访问请求，否则，纹理单元至少经由第二部分处理存储器访问请求 纹理处理流水线。 所公开方法的一个优点是可以将相同的处理和高速缓冲存储器用于纹理操作和对各种其他地址空间的加载/存储操作，导致减少的表面积和功率消耗。

公开(公告)号：US09292295B2

公开(公告)日：2016-03-22

申请号：US13914528

申请日：2013-06-10

Applicant: NVIDIA Corporation

Inventor： Philip Payman Shirvani ,  Peter Benjamin Sommers ,  Eric T. Anderson

IPC: G06F1/04 ,  G06F9/38

CPC classification number: G06F9/3871

Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Abstract translation: 公开了一种用于产生处理流水线的流量控制信号的系统，方法和计算机程序产品。 该方法包括以下步骤：通过第一流水线级基于从第二流水线级接收到的下游就绪信号和节流阻止信号产生延迟就绪信号。 基于上行有效信号和延迟就绪信号，由第一流水线级产生下行有效信号。 基于延迟就绪信号和下行有效信号，由第一流水线级产生上行就绪信号。

公开(公告)号：US20140168245A1

公开(公告)日：2014-06-19

申请号：US13720745

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Eric T. Anderson ,  Nick Barrow-Williams ,  Shirish Gadre ,  Joel James McCormack ,  Bryon S. Nordquist ,  Nirmal Raj Saxena ,  Lacky V. Shah

IPC: G06F13/14

CPC classification number: G06F13/14 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/36

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

公开(公告)号：US10043230B2

公开(公告)日：2018-08-07

申请号：US14033383

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Philip Payman Shirvani ,  Peter Sommers ,  Eric T. Anderson

IPC: G06T1/20 ,  G06F1/30

Abstract: Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.

公开(公告)号：US09348762B2

公开(公告)日：2016-05-24

申请号：US13720755

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Eric T. Anderson ,  Nick Barrow-Williams ,  Shirish Gadre ,  Joel James McCormack ,  Bryon S. Nordquist ,  Nirmal Raj Saxena ,  Lacky V. Shah

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1018

Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

Abstract translation: 配置为管理高速缓存单元的标签单元包括实现集合散列函数的聚结器。 集合散列函数将虚拟地址映射到特定的内容可寻址存储器单元（CAM）。 聚合器通过将虚拟地址分割成上部，中部和下部来实现集合散列函数。 上部分进一步分为偶数位和奇数索引位。 使用XOR树将偶数索引位减少到单个位，并且奇数索引以类似的方式减少。 这些单个位与虚拟地址的中间部分组合以提供识别特定CAM的CAM号码。 查询所识别的CAM以确定虚拟地址的标签部分的存在，指示高速缓存命中或高速缓存未命中。

公开(公告)号：US20140365750A1

公开(公告)日：2014-12-11

申请号：US13914528

申请日：2013-06-10

Applicant: NVIDIA Corporation

Inventor： Philip Payman Shirvani ,  Peter Benjamin Sommers ,  Eric T. Anderson

IPC: G06F9/38

CPC classification number: G06F9/3871

Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Abstract translation: 公开了一种用于产生处理流水线的流量控制信号的系统，方法和计算机程序产品。 该方法包括以下步骤：通过第一流水线级基于从第二流水线级接收到的下游就绪信号和节流阻止信号产生延迟就绪信号。 基于上行有效信号和延迟就绪信号，由第一流水线级产生下行有效信号。 基于延迟就绪信号和下行有效信号，由第一流水线级产生上行就绪信号。