公开(公告)号：US20200064894A1

公开(公告)日：2020-02-27

申请号：US16108006

申请日：2018-08-21

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith LI ,  Thomas E. DEWEY ,  Arthur CHEN ,  Simon LAI ,  Amit PABALKAR ,  Santosh NAYAK

IPC: G06F1/26 ,  G06F1/08 ,  G06F9/4401

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US20190163254A1

公开(公告)日：2019-05-30

申请号：US16175191

申请日：2018-10-30

Applicant: NVIDIA Corporation

Inventor： Thomas E. DEWEY ,  Narayan KULSHRESTHA ,  Ramachandiran V ,  Sachin IDGUNJI ,  Lordson YUE

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F1/3296 ,  G06T15/00 ,  G06F13/42

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

公开(公告)号：US20250117065A1

公开(公告)日：2025-04-10

申请号：US18925469

申请日：2024-10-24

Applicant: NVIDIA CORPORATION

Inventor： Thomas E. DEWEY ,  Michael IRWIN ,  Simon LAI ,  Sau Yan Keith LI

IPC: G06F1/26

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

公开(公告)号：US20230214000A1

公开(公告)日：2023-07-06

申请号：US17961440

申请日：2022-10-06

Applicant: NVIDIA CORPORATION

Inventor： Thomas E. DEWEY ,  Michael IRWIN ,  Simon LAI ,  Sau Yan Keith LI

IPC: G06F1/3287 ,  G05B13/02

CPC classification number: G06F1/3287 ,  G05B13/028

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

公开(公告)号：US20230213996A1

公开(公告)日：2023-07-06

申请号：US17961435

申请日：2022-10-06

Applicant: NVIDIA CORPORATION

Inventor： Thomas E. DEWEY ,  Michael IRWIN ,  Simon LAI ,  Sau Yan Keith LI

IPC: G06F1/3234 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprises: determining a target sound level for the multi-processor computing device; determining one or more candidate fan speed combinations for a first fan associated with a first temperature-controlled device included in the multi-processor computing device and a second fan associated with a second temperature-controlled device included in the multi-processor computing device based on the target sound level; determining a temperature error for one of the first temperature-controlled device, the second temperature-controlled device, or a third temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value for one of the first temperature-controlled device, the second temperature-controlled device, or the third temperature-controlled device; determining a value for a first power setting associated with the first temperature-controlled device based on the temperature error; and causing the first temperature-controlled device to perform one or more operations based on the value for the first power setting.

公开(公告)号：US20210255680A1

公开(公告)日：2021-08-19

申请号：US17306654

申请日：2021-05-03

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith LI ,  Thomas E. DEWEY ,  Arthur CHEN ,  Simon LAI ,  Amit PABALKAR ,  Santosh NAYAK

IPC: G06F1/26 ,  G06F9/4401 ,  G06F1/08

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US20200042076A1

公开(公告)日：2020-02-06

申请号：US16049916

申请日：2018-07-31

Applicant: NVIDIA Corporation

Inventor： Sachin IDGUNJI ,  Ben Pei En TSAI ,  Jun (Alex) GU ,  James REILLEY ,  Thomas E. DEWEY

IPC: G06F1/32

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.

公开(公告)号：US20190163255A1

公开(公告)日：2019-05-30

申请号：US16175232

申请日：2018-10-30

Applicant: NVIDIA Corporation

Inventor： Thomas E. DEWEY ,  Narayan KULSHRESTHA ,  Ramachandiran V ,  Sachin IDGUNJI ,  Lordson YUE

IPC: G06F1/32 ,  G06T1/20 ,  G06F15/78 ,  G06F13/42

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.